Datasheet LTC2259-16 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 16-Bit, 80Msps Ultralow Power 1.8V ADC |
| Pages / Page | 30 / 5 — DIGITAL INPUTS AND OUTPUTS. The. denotes the specifi cations which apply … |
| File Format / Size | PDF / 371 Kb |
| Document Language | English |
DIGITAL INPUTS AND OUTPUTS. The. denotes the specifi cations which apply over the full operating
Model Line for this Datasheet
Text Version of Document
LTC2259-16
DIGITAL INPUTS AND OUTPUTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200 Ω IOH Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 μA COUT Output Capacitance (Note 8) 4 pF
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE-DATA RATE) OVDD = 1.8V
VOH High Level Output Voltage IO = –500μA l 1.750 1.790 V VOL Low Level Output Voltage IO = 500μA l 0.010 0.050 V
OVDD = 1.5V
VOH High Level Output Voltage IO = –500μA 1.488 V VOL Low Level Output Voltage IO = 500μA 0.010 V
OVDD = 1.2V
VOH High Level Output Voltage IO = –500μA 1.185 V VOL Low Level Output Voltage IO = 500μA 0.010 V
DIGITAL DATA OUTPUTS (LVDS MODE)
VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode l 247 350 454 mV 100Ω Differential Load, 1.75mA Mode 175 mV VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode l 1.125 1.250 1.375 V 100Ω Differential Load, 1.75mA Mode 1.250 V RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω
POWER REQUIREMENTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMOS Output Modes: Full Data Rate and Double-Data Rate
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.9 V IVDD Analog Supply Current DC Input l 49.2 58.1 mA Sine Wave Input 50.2 mA IOVDD Digital Supply Current Sine Wave Input, OVDD=1.2V 2.5 mA PDISS Power Dissipation DC Input l 89 105 mW Sine Wave Input, OVDD=1.2V 93 mW
LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.9 V IVDD Analog Supply Current Sine Wave Input l 53.8 63.5 mA IOVDD Digital Supply Current Sine Input, 1.75mA Mode l 20.7 26 mA (0VDD = 1.8V) Sine Input, 3.5mA Mode l 40.5 47.8 mA PDISS Power Dissipation Sine Input, 1.75mA Mode l 134 161 mW Sine Input, 3.5mA Mode l 170 201 mW
All Output Modes
PSLEEP Sleep Mode Power 0.5 mW PNAP Nap Mode Power 9 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 10 mW (No increase for Nap or Sleep Modes) 225916fa 5
DIGITAL INPUTS AND OUTPUTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200 Ω IOH Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 μA COUT Output Capacitance (Note 8) 4 pF
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE-DATA RATE) OVDD = 1.8V
VOH High Level Output Voltage IO = –500μA l 1.750 1.790 V VOL Low Level Output Voltage IO = 500μA l 0.010 0.050 V
OVDD = 1.5V
VOH High Level Output Voltage IO = –500μA 1.488 V VOL Low Level Output Voltage IO = 500μA 0.010 V
OVDD = 1.2V
VOH High Level Output Voltage IO = –500μA 1.185 V VOL Low Level Output Voltage IO = 500μA 0.010 V
DIGITAL DATA OUTPUTS (LVDS MODE)
VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode l 247 350 454 mV 100Ω Differential Load, 1.75mA Mode 175 mV VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode l 1.125 1.250 1.375 V 100Ω Differential Load, 1.75mA Mode 1.250 V RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω
POWER REQUIREMENTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMOS Output Modes: Full Data Rate and Double-Data Rate
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.9 V IVDD Analog Supply Current DC Input l 49.2 58.1 mA Sine Wave Input 50.2 mA IOVDD Digital Supply Current Sine Wave Input, OVDD=1.2V 2.5 mA PDISS Power Dissipation DC Input l 89 105 mW Sine Wave Input, OVDD=1.2V 93 mW
LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.9 V IVDD Analog Supply Current Sine Wave Input l 53.8 63.5 mA IOVDD Digital Supply Current Sine Input, 1.75mA Mode l 20.7 26 mA (0VDD = 1.8V) Sine Input, 3.5mA Mode l 40.5 47.8 mA PDISS Power Dissipation Sine Input, 1.75mA Mode l 134 161 mW Sine Input, 3.5mA Mode l 170 201 mW
All Output Modes
PSLEEP Sleep Mode Power 0.5 mW PNAP Nap Mode Power 9 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 10 mW (No increase for Nap or Sleep Modes) 225916fa 5
