Datasheet LTC2259-16 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 16-Bit, 80Msps Ultralow Power 1.8V ADC |
| Pages / Page | 30 / 6 — TIMING CHARACTERISTICS. The. denotes the specifi cations which apply over … |
| File Format / Size | PDF / 371 Kb |
| Document Language | English |
TIMING CHARACTERISTICS. The. denotes the specifi cations which apply over the full operating temperature
Model Line for this Datasheet
Text Version of Document
LTC2259-16
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 1 80 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 5.93 6.25 500 ns Duty Cycle Stabilizer On l 2.00 6.25 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 5.93 6.25 500 ns Duty Cycle Stabilizer On l 2.00 6.25 500 ns tAP Sample-and-Hold Acquisition Delay 0 ns Time
Digital Data Outputs (CMOS Modes: Full Data Rate and Double-Data Rate)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode 5.0 Cycles Double-Data Rate Mode 5.5 Cycles
Digital Data Outputs (LVDS Mode)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.8 3.2 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.5 2.7 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency 5.5 Cycles
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode l 40 ns Readback Mode, CSDO = 20pF, RPULLUP = 2k l 250 ns tS CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
VDD = OVDD = 1.8V, fSAMPLE = 80MHz, LVDS outputs with internal may cause permanent damage to the device. Exposure to any Absolute termination disabled, differential ENC+/ENC– = 2VP-P sine wave, input Maximum Rating condition for extended periods may affect device range = 2VP-P with differential drive, unless otherwise noted. reliability and lifetime.
Note 6:
Integral nonlinearity is defi ned as the deviation of a code from a
Note 2:
All voltage values are with respect to GND with GND and OGND best fi t straight line to the transfer curve. The deviation is measured from shorted (unless otherwise noted). the center of the quantization band.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 7:
Offset error is the offset voltage measured from –0.5 LSB when will be clamped by internal diodes. This product can handle input currents the output code fl ickers between 0000 0000 0000 0000 and 1111 1111 of greater than 100mA below GND or above VDD without latchup. 1111 1111 in 2’s complement output mode.
Note 4:
When these pin voltages are taken below GND they will be
Note 8:
Guaranteed by design, not subject to test. clamped by internal diodes. When these pin voltages are taken above VDD
Note 9:
VDD = 1.8V, fSAMPLE = 80MHz, ENC+ = single-ended 1.8V square they will not be clamped by internal diodes. This product can handle input wave, ENC– = 0V, input range = 2VP-P with differential drive, 5pF load on currents of greater than 100mA below GND without latchup. each digital output unless otherwise noted.
Note 10:
Recommended operating conditions. 225916fa 6
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 1 80 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 5.93 6.25 500 ns Duty Cycle Stabilizer On l 2.00 6.25 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 5.93 6.25 500 ns Duty Cycle Stabilizer On l 2.00 6.25 500 ns tAP Sample-and-Hold Acquisition Delay 0 ns Time
Digital Data Outputs (CMOS Modes: Full Data Rate and Double-Data Rate)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode 5.0 Cycles Double-Data Rate Mode 5.5 Cycles
Digital Data Outputs (LVDS Mode)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.8 3.2 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.5 2.7 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency 5.5 Cycles
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode l 40 ns Readback Mode, CSDO = 20pF, RPULLUP = 2k l 250 ns tS CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
VDD = OVDD = 1.8V, fSAMPLE = 80MHz, LVDS outputs with internal may cause permanent damage to the device. Exposure to any Absolute termination disabled, differential ENC+/ENC– = 2VP-P sine wave, input Maximum Rating condition for extended periods may affect device range = 2VP-P with differential drive, unless otherwise noted. reliability and lifetime.
Note 6:
Integral nonlinearity is defi ned as the deviation of a code from a
Note 2:
All voltage values are with respect to GND with GND and OGND best fi t straight line to the transfer curve. The deviation is measured from shorted (unless otherwise noted). the center of the quantization band.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 7:
Offset error is the offset voltage measured from –0.5 LSB when will be clamped by internal diodes. This product can handle input currents the output code fl ickers between 0000 0000 0000 0000 and 1111 1111 of greater than 100mA below GND or above VDD without latchup. 1111 1111 in 2’s complement output mode.
Note 4:
When these pin voltages are taken below GND they will be
Note 8:
Guaranteed by design, not subject to test. clamped by internal diodes. When these pin voltages are taken above VDD
Note 9:
VDD = 1.8V, fSAMPLE = 80MHz, ENC+ = single-ended 1.8V square they will not be clamped by internal diodes. This product can handle input wave, ENC– = 0V, input range = 2VP-P with differential drive, 5pF load on currents of greater than 100mA below GND without latchup. each digital output unless otherwise noted.
Note 10:
Recommended operating conditions. 225916fa 6
