Datasheet LTC2259-16 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 16-Bit, 80Msps Ultralow Power 1.8V ADC |
| Pages / Page | 30 / 7 — TIMING DIAGRAMS. Full-Rate CMOS Output Mode Timing. All Outputs Are … |
| File Format / Size | PDF / 371 Kb |
| Document Language | English |
TIMING DIAGRAMS. Full-Rate CMOS Output Mode Timing. All Outputs Are Single-Ended and Have CMOS Levels
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LTC2259-16
TIMING DIAGRAMS Full-Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels
tAP N + 2 N + 4 ANALOG N INPUT N + 3 tH N + 1 tL ENC– ENC+ tD D0-D15 N – 5 N – 4 N – 3 N – 2 N – 1 tC CLKOUT+ CLKOUT– 225916 TD01
Double-Data Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels
tAP N + 2 N + 4 ANALOG N INPUT N + 3 tH N + 1 tL ENC– ENC+ tD tD D0_1 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2 ••• D14_15 D14N-5 D15N-5 D14N-4 D15N-4 D14N-3 D15N-3 D14N-2 D15N-2 tC tC CLKOUT+ CLKOUT– 225916 TD02 225916fa 7
TIMING DIAGRAMS Full-Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels
tAP N + 2 N + 4 ANALOG N INPUT N + 3 tH N + 1 tL ENC– ENC+ tD D0-D15 N – 5 N – 4 N – 3 N – 2 N – 1 tC CLKOUT+ CLKOUT– 225916 TD01
Double-Data Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels
tAP N + 2 N + 4 ANALOG N INPUT N + 3 tH N + 1 tL ENC– ENC+ tD tD D0_1 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2 ••• D14_15 D14N-5 D15N-5 D14N-4 D15N-4 D14N-3 D15N-3 D14N-2 D15N-2 tC tC CLKOUT+ CLKOUT– 225916 TD02 225916fa 7
