Datasheet LTC2269 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 16-Bit, 20Msps Low Noise ADC |
| Pages / Page | 32 / 9 — TIMING DIAGRAMS. Double Data Rate CMOS Output Mode Timing. All Outputs … |
| File Format / Size | PDF / 775 Kb |
| Document Language | English |
TIMING DIAGRAMS. Double Data Rate CMOS Output Mode Timing. All Outputs are Single-Ended and Have CMOS Levels
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LTC2269
TIMING DIAGRAMS Double Data Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels
tAP N + 2 N + 4 ANALOG N INPUT N + 3 tH N + 1 tL ENC– ENC+ tD tD D0_1 D0N-6 D1N-6 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 ttt D14_15 D14N-6 D15N-6 D14N-5 D15N-5 D14N-4 D15N-4 D14N-3 D15N-3 OF OFN-6 OFN-5 OFN-4 OFN-3 tC tC CLKOUT+ CLKOUT– 2269 TD02
Double Data Rate LVDS Output Mode Timing All Outputs are Differential and Have LVDS Levels
tAP N + 2 N + 4 ANALOG N INPUT N + 3 tH N + 1 tL ENC– ENC+ tD tD D0_1+ D0N-6 D1N-6 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0_1– ttt D14_15+ D14N-6 D15N-6 D14N-5 D15N-5 D14N-4 D15N-4 D14N-3 D15N-3 D14_15– OF+ OFN-6 OFN-5 OFN-4 OFN-3 OF– tC tC CLKOUT+ CLKOUT– 2269 TD03 2269f 9
TIMING DIAGRAMS Double Data Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels
tAP N + 2 N + 4 ANALOG N INPUT N + 3 tH N + 1 tL ENC– ENC+ tD tD D0_1 D0N-6 D1N-6 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 ttt D14_15 D14N-6 D15N-6 D14N-5 D15N-5 D14N-4 D15N-4 D14N-3 D15N-3 OF OFN-6 OFN-5 OFN-4 OFN-3 tC tC CLKOUT+ CLKOUT– 2269 TD02
Double Data Rate LVDS Output Mode Timing All Outputs are Differential and Have LVDS Levels
tAP N + 2 N + 4 ANALOG N INPUT N + 3 tH N + 1 tL ENC– ENC+ tD tD D0_1+ D0N-6 D1N-6 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0_1– ttt D14_15+ D14N-6 D15N-6 D14N-5 D15N-5 D14N-4 D15N-4 D14N-3 D15N-3 D14_15– OF+ OFN-6 OFN-5 OFN-4 OFN-3 OF– tC tC CLKOUT+ CLKOUT– 2269 TD03 2269f 9
