Datasheet LTC2380-16 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 16-Bit, 2Msps, Low Power SAR ADC with 96.2dB SNR |
| Pages / Page | 26 / 5 — ADC TIMING CHARACTERISTICS. The. denotes the specifications which apply … |
| File Format / Size | PDF / 694 Kb |
| Document Language | English |
ADC TIMING CHARACTERISTICS. The. denotes the specifications which apply over the full operating
Model Line for this Datasheet
- LTC2380CDE-16#PBF LTC2380CDE-16#PBF LTC2380CDE-16#TRPBF LTC2380CDE-16#TRPBF LTC2380CMS-16#PBF LTC2380CMS-16#PBF LTC2380CMS-16#TRPBF LTC2380CMS-16#TRPBF LTC2380HMS-16#PBF LTC2380HMS-16#PBF LTC2380HMS-16#TRPBF LTC2380HMS-16#TRPBF LTC2380IDE-16#PBF LTC2380IDE-16#PBF LTC2380IDE-16#TRPBF LTC2380IDE-16#TRPBF LTC2380IMS-16#PBF LTC2380IMS-16#PBF LTC2380IMS-16#TRPBF LTC2380IMS-16#TRPBF
Text Version of Document
LTC2380-16
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK↑ (Note 11) l 4 ns tHSDISCK SDI Hold Time From SCK↑ (Note 11) l 1 ns tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l 13.5 ns tDSDO SDO Data Valid Delay from SCK↑ CL = 20pF (Note 11) l 9.5 ns tHSDO SDO Data Remains Valid Delay from SCK↑ CL = 20pF (Note 10) l 1 ns tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 20pF (Note 10) l 5 ns tEN Bus Enable Time After RDL↓ (Note 11) l 16 ns tDIS Bus Relinquish Time After RDL↑ (Note 11) l 13 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve. Maximum Rating condition for extended periods may effect device The deviation is measured from the center of the quantization band. reliability and lifetime.
Note 7:
Bipolar zero-scale error is the offset voltage measured from
Note 2:
All voltage values are with respect to ground. –0.5LSB when the output code flickers between 0000 0000 0000 0000 and
Note 3:
When these pin voltages are taken below ground or above REF or 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS OV or +FS untrimmed deviation from ideal first and last code transitions and DD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above REF or OV includes the effect of offset error. DD without latch-up.
Note 8:
All specifications in dB are referred to a full-scale ±5V input with a
Note 4:
V 5V reference voltage. DD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 2MHz, REF/DGC = VREF.
Note 9:
fSMPL = 2MHz, IREF varies proportionately with sample rate.
Note 5:
Recommended operating conditions.
Note 10:
Guaranteed by design, not subject to test.
Note 11:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V and OVDD = 5.25V.
Note 12:
tSCK of 10ns maximum allows a shift clock frequency up to 100MHz for rising capture. 0.8*OVDD tWIDTH 0.2*OVDD t tDELAY 50% 50% DELAY 238016 F01 0.8*OVDD 0.8*OVDD 0.2*OVDD 0.2*OVDD
Figure 1. Voltage Levels for Timing Specifications
238016fb For more information www.linear.com/LTC2380-16 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Typical Application Related Parts
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK↑ (Note 11) l 4 ns tHSDISCK SDI Hold Time From SCK↑ (Note 11) l 1 ns tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l 13.5 ns tDSDO SDO Data Valid Delay from SCK↑ CL = 20pF (Note 11) l 9.5 ns tHSDO SDO Data Remains Valid Delay from SCK↑ CL = 20pF (Note 10) l 1 ns tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 20pF (Note 10) l 5 ns tEN Bus Enable Time After RDL↓ (Note 11) l 16 ns tDIS Bus Relinquish Time After RDL↑ (Note 11) l 13 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve. Maximum Rating condition for extended periods may effect device The deviation is measured from the center of the quantization band. reliability and lifetime.
Note 7:
Bipolar zero-scale error is the offset voltage measured from
Note 2:
All voltage values are with respect to ground. –0.5LSB when the output code flickers between 0000 0000 0000 0000 and
Note 3:
When these pin voltages are taken below ground or above REF or 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS OV or +FS untrimmed deviation from ideal first and last code transitions and DD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above REF or OV includes the effect of offset error. DD without latch-up.
Note 8:
All specifications in dB are referred to a full-scale ±5V input with a
Note 4:
V 5V reference voltage. DD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 2MHz, REF/DGC = VREF.
Note 9:
fSMPL = 2MHz, IREF varies proportionately with sample rate.
Note 5:
Recommended operating conditions.
Note 10:
Guaranteed by design, not subject to test.
Note 11:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V and OVDD = 5.25V.
Note 12:
tSCK of 10ns maximum allows a shift clock frequency up to 100MHz for rising capture. 0.8*OVDD tWIDTH 0.2*OVDD t tDELAY 50% 50% DELAY 238016 F01 0.8*OVDD 0.8*OVDD 0.2*OVDD 0.2*OVDD
Figure 1. Voltage Levels for Timing Specifications
238016fb For more information www.linear.com/LTC2380-16 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Typical Application Related Parts
