Datasheet LTC2389-16 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 16-Bit, 2.5Msps SAR ADC with Pin-Configurable Analog Input Range and 96dB SNR |
| Pages / Page | 40 / 6 — t iming characteristics The. denotes the specifications which apply over … |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
t iming characteristics The. denotes the specifications which apply over the full operating temperature
Model Line for this Datasheet
Text Version of Document
LTC2389-16
t iming characteristics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
tHSDI SDI Hold Time From SCK↓ l 1 ns tDSDO SDO Data Valid Delay From SCK↑ CL = 15pF l 9 ns tHSDO SDO Data Remains Valid Delay From SCK↑ CL = 15pF l 1 ns tDDBUSYL Data Valid to BUSY↓ CL = 15pF l 1 ns tEN Bus Enable Time After CS↓ l 11 ns tDDA1 Data Valid Delay From A1 Transition CL = 15pF l 8 ns tDIS Bus Relinquish Time After CS↑ l 11 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings zero-scale error is the offset voltage measured from 0.5LSB when the may cause permanent damage to the device. Exposure to any Absolute output code flickers between 0000 0000 0000 0000 and 0000 0000 Maximum Rating condition for extended periods may affect device 0000 0001. Bipolar zero-scale error is the offset voltage measured from reliability and lifetime. –0.5LSB when the output code flickers between 0000 0000 0000 0000 and
Note 2:
All voltage values are with respect to ground. 1111 1111 1111 1111. Fully differential full-scale error is the worst-case
Note 3:
When these pin voltages are taken below ground or above deviation of the first and last code transitions from ideal and includes the V effect of offset error. Unipolar full-scale error is the deviation of the last DD or OVDD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground, or above V code transition from ideal and includes the effect of offset error. Bipolar DD or OVDD, without latchup. full-scale error is the worst-case deviation of the first and last code transitions from ideal and includes the effect of offset error.
Note 4:
VDD = 5V, OVDD = 5V, VREF = 4.096V external reference, f
Note 8:
All specifications in dB are referred to a full-scale ±4.096V (fully SMPL = 2.5MHz, unless otherwise noted. differential), 0V to 4.096V (pseudo-differential unipolar), or ±2.048V
Note 5:
Recommended operating conditions. (pseudo-differential bipolar) input with a 4.096V reference voltage.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a
Note 9:
Temperature coefficient is calculated by dividing the maximum straight line passing through the actual endpoints of the transfer curve. change in output voltage by the specified temperature range. The deviation is measured from the center of the quantization band.
Note 10:
Guaranteed by design, not subject to test.
Note 7:
Fully differential zero-scale error is the offset voltage measured from –0.5LSB when the output code flickers between 0000 0000 0000
Note 11:
A tSCK period of 10ns minimum allows a shift clock frequency of 0000 and 1111 1111 1111 1111 in two’s complement format. Unipolar up to 100MHz for rising capture. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 238916 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
238916f 6 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Analog Input Converter Characteristics Dynamic Accuracy Reference Characteristics Digital Inputs And Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Package Description Related Parts Typical Application
t iming characteristics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
tHSDI SDI Hold Time From SCK↓ l 1 ns tDSDO SDO Data Valid Delay From SCK↑ CL = 15pF l 9 ns tHSDO SDO Data Remains Valid Delay From SCK↑ CL = 15pF l 1 ns tDDBUSYL Data Valid to BUSY↓ CL = 15pF l 1 ns tEN Bus Enable Time After CS↓ l 11 ns tDDA1 Data Valid Delay From A1 Transition CL = 15pF l 8 ns tDIS Bus Relinquish Time After CS↑ l 11 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings zero-scale error is the offset voltage measured from 0.5LSB when the may cause permanent damage to the device. Exposure to any Absolute output code flickers between 0000 0000 0000 0000 and 0000 0000 Maximum Rating condition for extended periods may affect device 0000 0001. Bipolar zero-scale error is the offset voltage measured from reliability and lifetime. –0.5LSB when the output code flickers between 0000 0000 0000 0000 and
Note 2:
All voltage values are with respect to ground. 1111 1111 1111 1111. Fully differential full-scale error is the worst-case
Note 3:
When these pin voltages are taken below ground or above deviation of the first and last code transitions from ideal and includes the V effect of offset error. Unipolar full-scale error is the deviation of the last DD or OVDD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground, or above V code transition from ideal and includes the effect of offset error. Bipolar DD or OVDD, without latchup. full-scale error is the worst-case deviation of the first and last code transitions from ideal and includes the effect of offset error.
Note 4:
VDD = 5V, OVDD = 5V, VREF = 4.096V external reference, f
Note 8:
All specifications in dB are referred to a full-scale ±4.096V (fully SMPL = 2.5MHz, unless otherwise noted. differential), 0V to 4.096V (pseudo-differential unipolar), or ±2.048V
Note 5:
Recommended operating conditions. (pseudo-differential bipolar) input with a 4.096V reference voltage.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a
Note 9:
Temperature coefficient is calculated by dividing the maximum straight line passing through the actual endpoints of the transfer curve. change in output voltage by the specified temperature range. The deviation is measured from the center of the quantization band.
Note 10:
Guaranteed by design, not subject to test.
Note 7:
Fully differential zero-scale error is the offset voltage measured from –0.5LSB when the output code flickers between 0000 0000 0000
Note 11:
A tSCK period of 10ns minimum allows a shift clock frequency of 0000 and 1111 1111 1111 1111 in two’s complement format. Unipolar up to 100MHz for rising capture. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 238916 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
238916f 6 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Analog Input Converter Characteristics Dynamic Accuracy Reference Characteristics Digital Inputs And Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Package Description Related Parts Typical Application
