Datasheet LTC2433-1 (Analog Devices) - 5

LTC2433-1
W U TI I G CHARACTERISTICS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fEOSC External Oscillator Frequency Range ● 2.56 2000 kHz tHEO External Oscillator High Period ● 0.25 390 µs tLEO External Oscillator Low Period ● 0.25 390 µs tCONV Conversion Time FO = 0V ● 143.8 146.7 149.6 ms External Oscillator (Note 10) ● 20510/fEOSC (in kHz) ms fISCK Internal SCK Frequency Internal Oscillator (Note 9) 17.5 kHz External Oscillator (Notes 9, 10) fEOSC/8 kHz DISCK Internal SCK Duty Cycle (Note 9) ● 45 55 % fESCK External SCK Frequency Range (Note 8) ● 2000 kHz tLESCK External SCK Low Period (Note 8) ● 250 ns tHESCK External SCK High Period (Note 8) ● 250 ns tDOUT_ISCK Internal SCK 19-Bit Data Output Time Internal Oscillator (Notes 9, 11) ● 1.06 1.09 1.11 ms External Oscillator (Notes 9, 10) ● 152/fEOSC (in kHz) ms tDOUT_ESCK External SCK 19-Bit Data Output Time (Note 8) ● 19/fESCK (in kHz) ms t1 CS ↓ to SDO Low Z ● 0 200 ns t2 CS ↑ to SDO High Z ● 0 200 ns t3 CS ↓ to SCK ↓ (Note 9) ● 0 200 ns t4 CS ↓ to SCK ↑ (Note 8) ● 50 ns tKQMAX SCK ↓ to SDO Valid ● 220 ns tKQMIN SDO Hold After SCK ↓ (Note 5) ● 15 ns t5 SCK Set-Up Before CS ↓ ● 50 ns t6 SCK Hold After CS ↓ ● 50 ns
Note 1:
Absolute Maximum Ratings are those values beyond which the
Note 9:
The converter is in internal SCK mode of operation such that life of the device may be impaired. the SCK pin is used as digital output. In this mode of operation the SCK pin has a total equivalent load capacitance C
Note 2:
All voltage values are with respect to GND. LOAD = 20pF.
Note 10:
The external oscillator is connected to the F
Note 3:
V O pin. The external CC = 2.7V to 5.5V unless otherwise specified. oscillator frequency, f V EOSC, is expressed in kHz. REF = REF+ – REF–, VREFCM = (REF+ + REF–)/2; VIN = IN+ – IN –, VINCM = (IN+ + IN–)/2.
Note 11:
The converter uses the internal oscillator. F
Note 4:
F O = 0V. O pin tied to GND or to an external conversion clock source with fEOSC = 139,800Hz unless otherwise specified.
Note 12:
1.45µV RMS noise is independent of VREF. Since the noise performance is limited by the quantization, lowering V
Note 5:
Guaranteed by design, not subject to test. REF improves the effective resolution.
Note 6:
Integral nonlinearity is defined as the deviation of a code from
Note 13:
Guaranteed by design and test correlation. a precise analog input voltage. Maximum specifications are limited by the LSB step size (VREF/216) and the single shot measurement. Typical
Note 14:
The low sleep mode current is valid only when CS is high. specifications are measured from the center of the quantization band.
Note 15:
These parameters are guaranteed by design over the full
Note 7:
FO = GND (internal oscillator) or fEOSC = 139,800Hz ±2% supply and temperature range. Automated testing procedures are (external oscillator). limited by the LSB step size (VREF/65,536).
Note 8:
The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in kHz. 24331fa 5