Datasheet LTC2433-1 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Differential Input 16-Bit No Latency Delta Sigma ADC |
| Pages / Page | 28 / 6 — PI FU CTIO S. VCC (Pin 1):. SDO (Pin 8):. REF+ (Pin 2), REF– (Pin 3):. … |
| File Format / Size | PDF / 306 Kb |
| Document Language | English |
PI FU CTIO S. VCC (Pin 1):. SDO (Pin 8):. REF+ (Pin 2), REF– (Pin 3):. SCK (Pin 9):. IN+ (Pin 4), IN– (Pin 5):. GND (Pin 6):
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Text Version of Document
LTC2433-1
U U U PI FU CTIO S VCC (Pin 1):
Positive Supply Voltage. Bypass to GND with
SDO (Pin 8):
Three-State Digital Output. During the Data a 10µF tantalum capacitor in parallel with 0.1µF ceramic Output period, this pin is used as serial data output. When capacitor as close to the part as possible. the chip select CS is HIGH (CS = VCC) the SDO pin is in a high impedance state. During the Conversion and Sleep
REF+ (Pin 2), REF– (Pin 3):
Differential Reference Input. periods, this pin is used as the conversion status output. The voltage on these pins can have any value between GND The conversion status can be observed by pulling CS LOW. and VCC as long as the reference positive input, REF+, is maintained more positive than the reference negative
SCK (Pin 9):
Bidirectional Digital Clock Pin. In Internal input, REF –, by at least 0.1V. Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the Data
IN+ (Pin 4), IN– (Pin 5):
Differential Analog Input. The Output period. In External Serial Clock Operation mode, voltage on these analog inputs can have any value between SCK is used as digital input for the external serial interface GND and VCC. Within these limits the converter bipolar clock during the Data Output period. A weak internal pull- input range (VIN = IN+ – IN–) extends from – 0.5 • (VREF) up is automatically activated in Internal Serial Clock Op- to 0.5 • (VREF). Outside this input range the converter eration mode. The Serial Clock Operation mode is deter- produces unique overrange and underrange output codes. mined by the logic level applied to the SCK pin at power up
GND (Pin 6):
Ground. Connect this pin to a ground plane or during the most recent falling edge of CS. through a low impedance connection.
FO (Pin 10):
Frequency Control Pin. Digital input that
CS (Pin 7):
Active LOW Digital Input. A LOW on this pin controls the ADC’s notch frequencies and conversion enables the SDO digital output and wakes up the ADC. time. When the FO pin is connected to GND (FO = 0V), the Following each conversion the ADC automatically enters converter uses its internal oscillator and rejects 50Hz and the Sleep mode and remains in this low power state as 60Hz simultaneously. When FO is driven by an external long as CS is HIGH. A LOW-to-HIGH transition on CS clock signal with a frequency fEOSC, the converter uses this during the Data Output transfer aborts the data transfer signal as its system clock and the digital filter has 87dB and starts a new conversion. minimum rejection in the range fEOSC/2560 ±14% and 110dB minimum rejection at fEOSC/2560 ±4%. 24331fa 6
U U U PI FU CTIO S VCC (Pin 1):
Positive Supply Voltage. Bypass to GND with
SDO (Pin 8):
Three-State Digital Output. During the Data a 10µF tantalum capacitor in parallel with 0.1µF ceramic Output period, this pin is used as serial data output. When capacitor as close to the part as possible. the chip select CS is HIGH (CS = VCC) the SDO pin is in a high impedance state. During the Conversion and Sleep
REF+ (Pin 2), REF– (Pin 3):
Differential Reference Input. periods, this pin is used as the conversion status output. The voltage on these pins can have any value between GND The conversion status can be observed by pulling CS LOW. and VCC as long as the reference positive input, REF+, is maintained more positive than the reference negative
SCK (Pin 9):
Bidirectional Digital Clock Pin. In Internal input, REF –, by at least 0.1V. Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the Data
IN+ (Pin 4), IN– (Pin 5):
Differential Analog Input. The Output period. In External Serial Clock Operation mode, voltage on these analog inputs can have any value between SCK is used as digital input for the external serial interface GND and VCC. Within these limits the converter bipolar clock during the Data Output period. A weak internal pull- input range (VIN = IN+ – IN–) extends from – 0.5 • (VREF) up is automatically activated in Internal Serial Clock Op- to 0.5 • (VREF). Outside this input range the converter eration mode. The Serial Clock Operation mode is deter- produces unique overrange and underrange output codes. mined by the logic level applied to the SCK pin at power up
GND (Pin 6):
Ground. Connect this pin to a ground plane or during the most recent falling edge of CS. through a low impedance connection.
FO (Pin 10):
Frequency Control Pin. Digital input that
CS (Pin 7):
Active LOW Digital Input. A LOW on this pin controls the ADC’s notch frequencies and conversion enables the SDO digital output and wakes up the ADC. time. When the FO pin is connected to GND (FO = 0V), the Following each conversion the ADC automatically enters converter uses its internal oscillator and rejects 50Hz and the Sleep mode and remains in this low power state as 60Hz simultaneously. When FO is driven by an external long as CS is HIGH. A LOW-to-HIGH transition on CS clock signal with a frequency fEOSC, the converter uses this during the Data Output transfer aborts the data transfer signal as its system clock and the digital filter has 87dB and starts a new conversion. minimum rejection in the range fEOSC/2560 ±14% and 110dB minimum rejection at fEOSC/2560 ±4%. 24331fa 6
