Datasheet LTC2436-1 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 2-Channel Differential Input 16-Bit No Latency ∆Σ™ ADC |
| Pages / Page | 28 / 6 — PI FU CTIO S. VCC (Pin 1):. REF+ (Pin 2), REF– (Pin 3):. SDO (Pin 12):. … |
| File Format / Size | PDF / 304 Kb |
| Document Language | English |
PI FU CTIO S. VCC (Pin 1):. REF+ (Pin 2), REF– (Pin 3):. SDO (Pin 12):. CH0+ (Pin 4):. SCK (Pin 13):. CH0– (Pin 5):. CH1+ (Pin 6):
Model Line for this Datasheet
Text Version of Document
LTC2436-1
U U U PI FU CTIO S VCC (Pin 1):
Positive Supply Voltage. Bypass to GND with long as CS is HIGH. A LOW-to-HIGH transition on CS a 10µF tantalum capacitor in parallel with 0.1µF ceramic during the Data Output transfer aborts the data transfer capacitor as close to the part as possible. and starts a new conversion.
REF+ (Pin 2), REF– (Pin 3):
Differential Reference Input.
SDO (Pin 12):
Three-State Digital Output. During the Data The voltage on these pins can have any value between GND Output period, this pin is used as serial data output. When and VCC as long as the reference positive input, REF+, is the chip select CS is HIGH (CS = VCC) the SDO pin is in a maintained more positive than the reference negative high impedance state. During the Conversion and Sleep input, REF –, by at least 0.1V. periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW.
CH0+ (Pin 4):
Positive Input for Differential Channel 0.
SCK (Pin 13):
Bidirectional Digital Clock Pin. In Internal
CH0– (Pin 5):
Negative Input for Differential Channel 0. Serial Clock Operation mode, SCK is used as digital output
CH1+ (Pin 6):
Positive Input for Differential Channel 1. for the internal serial interface clock during the Data
CH1– (Pin 7):
Negative Input for Differential Channel 1. Output period. In External Serial Clock Operation mode, The voltage on these four analog inputs (Pins 4 to 7) can SCK is used as digital input for the external serial interface have any value between GND and V clock during the Data Output period. A weak internal pull- CC. Within these limits the converter bipolar input range (V up is automatically activated in Internal Serial Clock Op- IN = IN+ – IN–) extends from – 0.5 • (V eration mode. The Serial Clock Operation mode is deter- REF ) to 0.5 • (VREF ). Outside this input range the converter produces unique overrange and underrange mined by the logic level applied to the SCK pin at power up output codes. or during the most recent falling edge of CS.
GND (Pins 8, 9, 10, 15, 16):
Ground. Multiple ground pins
FO (Pin 14):
Frequency Control Pin. Digital input that internally connected for optimum ground current flow and controls the ADC’s notch frequencies and conversion V time. When the F CC decoupling. Connect each one of these pins to a ground O pin is connected to GND (FO = 0V), the plane through a low impedance connection. All five pins must converter uses its internal oscillator and rejects 50Hz and be connected to ground for proper operation. 60Hz simultaneously. When FO is driven by an external clock signal with a frequency fEOSC, the converter uses this
CS (Pin 11):
Active LOW Digital Input. A LOW on this pin signal as its system clock and the digital filter has 87dB enables the SDO digital output and wakes up the ADC. minimum rejection in the range fEOSC/2560 ±14% and Following each conversion the ADC automatically enters 110dB minimum rejection at fEOSC/2560 ±4%. the Sleep mode and remains in this low power state as 24361f 6
U U U PI FU CTIO S VCC (Pin 1):
Positive Supply Voltage. Bypass to GND with long as CS is HIGH. A LOW-to-HIGH transition on CS a 10µF tantalum capacitor in parallel with 0.1µF ceramic during the Data Output transfer aborts the data transfer capacitor as close to the part as possible. and starts a new conversion.
REF+ (Pin 2), REF– (Pin 3):
Differential Reference Input.
SDO (Pin 12):
Three-State Digital Output. During the Data The voltage on these pins can have any value between GND Output period, this pin is used as serial data output. When and VCC as long as the reference positive input, REF+, is the chip select CS is HIGH (CS = VCC) the SDO pin is in a maintained more positive than the reference negative high impedance state. During the Conversion and Sleep input, REF –, by at least 0.1V. periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW.
CH0+ (Pin 4):
Positive Input for Differential Channel 0.
SCK (Pin 13):
Bidirectional Digital Clock Pin. In Internal
CH0– (Pin 5):
Negative Input for Differential Channel 0. Serial Clock Operation mode, SCK is used as digital output
CH1+ (Pin 6):
Positive Input for Differential Channel 1. for the internal serial interface clock during the Data
CH1– (Pin 7):
Negative Input for Differential Channel 1. Output period. In External Serial Clock Operation mode, The voltage on these four analog inputs (Pins 4 to 7) can SCK is used as digital input for the external serial interface have any value between GND and V clock during the Data Output period. A weak internal pull- CC. Within these limits the converter bipolar input range (V up is automatically activated in Internal Serial Clock Op- IN = IN+ – IN–) extends from – 0.5 • (V eration mode. The Serial Clock Operation mode is deter- REF ) to 0.5 • (VREF ). Outside this input range the converter produces unique overrange and underrange mined by the logic level applied to the SCK pin at power up output codes. or during the most recent falling edge of CS.
GND (Pins 8, 9, 10, 15, 16):
Ground. Multiple ground pins
FO (Pin 14):
Frequency Control Pin. Digital input that internally connected for optimum ground current flow and controls the ADC’s notch frequencies and conversion V time. When the F CC decoupling. Connect each one of these pins to a ground O pin is connected to GND (FO = 0V), the plane through a low impedance connection. All five pins must converter uses its internal oscillator and rejects 50Hz and be connected to ground for proper operation. 60Hz simultaneously. When FO is driven by an external clock signal with a frequency fEOSC, the converter uses this
CS (Pin 11):
Active LOW Digital Input. A LOW on this pin signal as its system clock and the digital filter has 87dB enables the SDO digital output and wakes up the ADC. minimum rejection in the range fEOSC/2560 ±14% and Following each conversion the ADC automatically enters 110dB minimum rejection at fEOSC/2560 ±4%. the Sleep mode and remains in this low power state as 24361f 6
