Datasheet LTC2436-1 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 2-Channel Differential Input 16-Bit No Latency ∆Σ™ ADC |
| Pages / Page | 28 / 10 — APPLICATIO S I FOR ATIO. Table 1. LTC2436-1 Status Bits. Bit 18. Bit 17. … |
| File Format / Size | PDF / 304 Kb |
| Document Language | English |
APPLICATIO S I FOR ATIO. Table 1. LTC2436-1 Status Bits. Bit 18. Bit 17. Bit 16 Bit 15. Input Range. EOC. CH0/CH1. SIG. MSB
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Text Version of Document
LTC2436-1
U U W U APPLICATIO S I FOR ATIO
Bit 18 (first output bit) is the end of conversion (EOC) remains high impedance and any externally generated indicator. This bit is available at the SDO pin during the SCK clock pulses are ignored by the internal data out shift conversion and sleep states whenever the CS pin is LOW. register. This bit is HIGH during the conversion and goes LOW In order to shift the conversion result out of the device, CS when the conversion is complete. must first be driven LOW. EOC is seen at the SDO pin of the Bit 17 (second output bit) is the selected channel indicator. device once CS is pulled LOW. EOC changes real time from The bit is LOW for channel 0 and HIGH for channel 1 HIGH to LOW at the completion of a conversion. This selected. signal may be used as an interrupt for an external micro- controller. Bit 18 (EOC) can be captured on the first rising Bit 16 (third output bit) is the conversion result sign indi- edge of SCK. Bit 17 is shifted out of the device on the first cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this falling edge of SCK. The final data bit (Bit 0) is shifted out bit is LOW. on the falling edge of the 18th SCK and may be latched on Bit 15 (fourth output bit) is the most significant bit (MSB) the rising edge of the 19th SCK pulse. On the falling edge of the result. This bit in conjunction with Bit 16 also of the 19th SCK pulse, SDO goes HIGH indicating the provides the underrange or overrange indication. If both initiation of a new conversion cycle. This bit serves as EOC Bit 16 and Bit 15 are HIGH, the differential input voltage is (Bit 18) for the next conversion cycle. Table 2 summarizes above +FS. If both Bit 16 and Bit 15 are LOW, the the output data format. differential input voltage is below –FS. In order to remain compatible with some SPI The function of these bits is summarized in Table 1. microcontrollers, more than 19 SCK clock pulses may be
Table 1. LTC2436-1 Status Bits
applied. As long as these clock edges are complete before
Bit 18 Bit 17 Bit 16 Bit 15
the conversion ends, they will not effect the serial data.
Input Range EOC CH0/CH1 SIG MSB
However, switching SCK during a conversion may gener- V ate ground currents in the device leading to extra offset IN ≥ 0.5 • VREF 0 0 or 1 1 1 0V ≤ V and noise error sources. IN < 0.5 • VREF 0 0 or 1 1 0 –0.5 • VREF ≤ VIN < 0V 0 0 or 1 0 1 As long as the voltage on the analog input pins is main- VIN < – 0.5 • VREF 0 0 or 1 0 0 tained within the – 0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any Bits 15-0 are the 16-Bit conversion result MSB first. differential input voltage VIN from –FS = –0.5 • VREF to Bit 0 is the least significant bit (LSB). +FS = 0.5 • VREF. For differential input voltages greater than Data is shifted out of the SDO pin under control of the serial +FS, the conversion result is clamped to the value corre- clock (SCK), see Figure 3. Whenever CS is HIGH, SDO sponding to the +FS + 1LSB. For differential input voltages CS BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 1 BIT 0 SDO EOC CH0/CH1 SIG MSB LSB16 Hi-Z SCK 1 2 3 4 5 17 18 19 SLEEP DATA OUTPUT CONVERSION 24361 F03
Figure 3. Output Data Timing
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U U W U APPLICATIO S I FOR ATIO
Bit 18 (first output bit) is the end of conversion (EOC) remains high impedance and any externally generated indicator. This bit is available at the SDO pin during the SCK clock pulses are ignored by the internal data out shift conversion and sleep states whenever the CS pin is LOW. register. This bit is HIGH during the conversion and goes LOW In order to shift the conversion result out of the device, CS when the conversion is complete. must first be driven LOW. EOC is seen at the SDO pin of the Bit 17 (second output bit) is the selected channel indicator. device once CS is pulled LOW. EOC changes real time from The bit is LOW for channel 0 and HIGH for channel 1 HIGH to LOW at the completion of a conversion. This selected. signal may be used as an interrupt for an external micro- controller. Bit 18 (EOC) can be captured on the first rising Bit 16 (third output bit) is the conversion result sign indi- edge of SCK. Bit 17 is shifted out of the device on the first cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this falling edge of SCK. The final data bit (Bit 0) is shifted out bit is LOW. on the falling edge of the 18th SCK and may be latched on Bit 15 (fourth output bit) is the most significant bit (MSB) the rising edge of the 19th SCK pulse. On the falling edge of the result. This bit in conjunction with Bit 16 also of the 19th SCK pulse, SDO goes HIGH indicating the provides the underrange or overrange indication. If both initiation of a new conversion cycle. This bit serves as EOC Bit 16 and Bit 15 are HIGH, the differential input voltage is (Bit 18) for the next conversion cycle. Table 2 summarizes above +FS. If both Bit 16 and Bit 15 are LOW, the the output data format. differential input voltage is below –FS. In order to remain compatible with some SPI The function of these bits is summarized in Table 1. microcontrollers, more than 19 SCK clock pulses may be
Table 1. LTC2436-1 Status Bits
applied. As long as these clock edges are complete before
Bit 18 Bit 17 Bit 16 Bit 15
the conversion ends, they will not effect the serial data.
Input Range EOC CH0/CH1 SIG MSB
However, switching SCK during a conversion may gener- V ate ground currents in the device leading to extra offset IN ≥ 0.5 • VREF 0 0 or 1 1 1 0V ≤ V and noise error sources. IN < 0.5 • VREF 0 0 or 1 1 0 –0.5 • VREF ≤ VIN < 0V 0 0 or 1 0 1 As long as the voltage on the analog input pins is main- VIN < – 0.5 • VREF 0 0 or 1 0 0 tained within the – 0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any Bits 15-0 are the 16-Bit conversion result MSB first. differential input voltage VIN from –FS = –0.5 • VREF to Bit 0 is the least significant bit (LSB). +FS = 0.5 • VREF. For differential input voltages greater than Data is shifted out of the SDO pin under control of the serial +FS, the conversion result is clamped to the value corre- clock (SCK), see Figure 3. Whenever CS is HIGH, SDO sponding to the +FS + 1LSB. For differential input voltages CS BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 1 BIT 0 SDO EOC CH0/CH1 SIG MSB LSB16 Hi-Z SCK 1 2 3 4 5 17 18 19 SLEEP DATA OUTPUT CONVERSION 24361 F03
Figure 3. Output Data Timing
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