Datasheet LTC2436-1 (Analog Devices) - 8

LTC2436-1
U U W U APPLICATIO S I FOR ATIO CONVERTER OPERATION
after the first rising edge of SCK, the device begins outputting the conversion result. Taking CS high at this
Converter Operation Cycle
point will terminate the data output state and start a new The LTC2436-1 is a low power, ∆Σ ADC with automatic conversion. There is no latency in the conversion result. alternate channel selection between the two differential The data output corresponds to the conversion just per- channels and an easy-to-use 3-wire serial interface (see formed. This result is shifted out on the serial data out pin Figure 1). Channel 0 is selected automatically at power up (SDO) under the control of the serial clock (SCK). Data is and the two channels are selected alternately afterwards updated on the falling edge of SCK allowing the user to (ping-pong). Its operation is made up of three states. The reliably latch data on the rising edge of SCK (see Figure 3). converter operating cycle begins with the conversion, The data output state is concluded once 19 bits are read followed by the low power sleep state and ends with the out of the ADC or when CS is brought HIGH. The device data output (see Figure 2). The 3-wire interface consists automatically initiates a new conversion and the cycle of serial data output (SDO), serial clock (SCK) and chip repeats. In order to maintain compatibility with 24-/32-bit select (CS). data transfers, it is possible to clock the LTC2436-1 with additional serial clock pulses. This results in additional Initially, the LTC2436-1 performs a conversion. Once the data bits which are always logic HIGH. conversion is complete, the device enters the sleep state. The part remains in the sleep state as long as CS is HIGH. Through timing control of the CS and SCK pins, the While in this sleep state, power consumption is reduced by LTC2436-1 offers several flexible modes of operation nearly two orders of magnitude. The conversion result is (internal or external SCK and free-running conversion held indefinitely in a static shift register while the converter modes). These various modes do not require program- is in the sleep state. ming configuration registers; moreover, they do not dis- turb the cyclic operation described above. These modes of Once CS is pulled LOW, the device exits the low power operation are described in detail in the Serial Interface mode and enters the data output state. If CS is pulled HIGH Timing Modes section. before the first rising edge of SCK, the device returns to the low power sleep mode and the conversion result is still
Conversion Clock
held in the internal static shift register. If CS remains LOW A major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter POWER UP (commonly implemented as a Sinc or Comb filter). For IN+ = CH0+, IN– = CH0– high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50Hz and CONVERT 60Hz plus their harmonics. The filter rejection perfor- mance is directly related to the accuracy of the converter SLEEP system clock. The LTC2436-1 incorporates a highly accu- rate on-chip oscillator. This eliminates the need for exter- nal frequency setting components such as crystals or FALSE oscillators. Clocked by the on-chip oscillator, the CS = LOW AND LTC2436-1 achieves a minimum of 87dB rejection over SCK the range 49Hz to 61.2Hz. TRUE DATA OUTPUT
Ease of Use
SWITCH CHANNEL 24361 F02 The LTC2436-1 data output has no latency, filter settling
Figure 2. LTC2436-1 State Transition Diagram
delay or redundant data associated with the conversion 24361f 8