LTC2439-1 FUNCTIONAL BLOCK DIAGRAM VCC AUTOCALIBRATION F REF+ O AND CONTROL INTERNAL (INT/EXT) REF– GND OSCILLATOR CH0 – + CH1 IN+ • DIFFERENTIAL SDI • MUX 3RD ORDER IN– SERIAL • SCK ∆Σ MODULATOR CH15 INTERFACE SDO COM CS DECIMATING FIR ADDRESS 24391 F01 Figure 1TEST CIRCUITS VCC SDO 1.69k 1.69k CLOAD = 20pF SDO 241418 TC01 CLOAD = 20pF Hi-Z TO VOH VOL TO VOH 241418 TC02 VOH TO Hi-Z Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z APPLICATIONS INFORMATION CONVERTER OPERATION POWER UP IN+ = CH0, IN– = CH1 Converter Operation Cycle The LTC2439-1 is a multichannel, low power, delta-sigma CONVERT analog-to-digital converter with an easy-to-use 4-wire serial interface (see Figure 1). Its operation is made up SLEEP of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data input/output (see Figure 2). The 4-wire FALSE CS = LOW interface consists of serial data input (SDI), serial data AND SCK output (SDO), serial clock (SCK) and chip select (CS). TRUE Initially, the LTC2439-1 performs a conversion. Once the DATA OUTPUT conversion is complete, the device enters the sleep state. ADDRESS INPUT The part remains in the sleep state as long as CS is HIGH. 24391 F02 While in the sleep state, power consumption is reduced by Figure 2. LTC2439-1 State Transition Diagram nearly two orders of magnitude. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. 24391fb For more information www.linear.com/LTC2439-1 7 Document Outline Features Applications Typical Application Absolute Maximum Ratings Order Information Electrical Characteristics Converter Characteristics Analog Input and Reference Digital Inputs and Digital Outputs POWER REQUIREMENTS Timing Characteristics Pin Functions FUNCTIONAL Block Diagram Test CircuitS Applications Information Package Description Revision History Typical Application Related Parts