Datasheet LTC2439-1 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 8-/16-Channel 16-Bit No Latency ∆Σ™ ADC |
| Pages / Page | 30 / 8 — APPLICATIONS INFORMATION. Figure 3a. Input/Output Data Timing. Figure 3b. … |
| File Format / Size | PDF / 583 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Figure 3a. Input/Output Data Timing. Figure 3b. Typical Operation Sequence
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LTC2439-1
APPLICATIONS INFORMATION
Once CS is pulled LOW, the device exits the low power user to reliably latch data on the rising edge of SCK (see mode and enters the data output state. If CS is pulled HIGH Figure 3). The data output state is concluded once 19 before the first rising edge of SCK, the device returns to bits are read out of the ADC or when CS is brought HIGH. the low power sleep mode and the conversion result is The device automatically initiates a new conversion and still held in the internal static shift register. If CS remains the cycle repeats. In order to maintain compatibility with LOW after the first rising edge of SCK, the device begins 24-/32-bit data transfers, it is possible to clock the outputting the conversion result and inputting channel LTC2439-1 with additional serial clock pulses. This results selection bits. Taking CS high at this point will terminate in additional data bits which are always logic HIGH. the data output state and start a new conversion. The channel selection control bits are shifted in through SDI Through timing control of the CS and SCK pins, the from the first rising edge of SCK and depending on the LTC2439-1 offers several flexible modes of operation control bits, the converter updates its channel selection (internal or external SCK and free-running conversion immediately and is valid for the next conversion. The details modes). These various modes do not require programming of channel selection control bits are described in the Input configuration registers; moreover, they do not disturb the Data Mode section. The output data is shifted out the SDO cyclic operation described above. These modes of opera- pin under the control of the serial clock (SCK). The output tion are described in detail in the Serial Interface Timing data is updated on the falling edge of SCK allowing the Modes section. CS BIT18 BIT17 BIT16 BIT15 BIT14 BIT13 BIT12 BIT11 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 SDO EOC (0) SIG MSB B22 LSB Hi-Z CONVERSON RESULT SCK SDI ODD/ (1) (0) EN SGL A2 A1 A0 DON’T CARE SIGN SLEEP DATA INPUT/OUTPUT CONVERSION 24391 F03a
Figure 3a. Input/Output Data Timing
CONVERSION RESULT CONVERSION RESULT CONVERSION RESULT N – 1 N N + 1 SDO Hi-Z Hi-Z Hi-Z SCK SDI DON’T CARE DON’T CARE ADDRESS ADDRESS ADDRESS N N + 1 N + 2 OUTPUT OUTPUT OUTPUT OPERATION N – 1 CONVERSION N N CONVERSION N + 1 N + 1 24391 F03b
Figure 3b. Typical Operation Sequence
24391fb 8 For more information www.linear.com/LTC2439-1 Document Outline Features Applications Typical Application Absolute Maximum Ratings Order Information Electrical Characteristics Converter Characteristics Analog Input and Reference Digital Inputs and Digital Outputs POWER REQUIREMENTS Timing Characteristics Pin Functions FUNCTIONAL Block Diagram Test CircuitS Applications Information Package Description Revision History Typical Application Related Parts
APPLICATIONS INFORMATION
Once CS is pulled LOW, the device exits the low power user to reliably latch data on the rising edge of SCK (see mode and enters the data output state. If CS is pulled HIGH Figure 3). The data output state is concluded once 19 before the first rising edge of SCK, the device returns to bits are read out of the ADC or when CS is brought HIGH. the low power sleep mode and the conversion result is The device automatically initiates a new conversion and still held in the internal static shift register. If CS remains the cycle repeats. In order to maintain compatibility with LOW after the first rising edge of SCK, the device begins 24-/32-bit data transfers, it is possible to clock the outputting the conversion result and inputting channel LTC2439-1 with additional serial clock pulses. This results selection bits. Taking CS high at this point will terminate in additional data bits which are always logic HIGH. the data output state and start a new conversion. The channel selection control bits are shifted in through SDI Through timing control of the CS and SCK pins, the from the first rising edge of SCK and depending on the LTC2439-1 offers several flexible modes of operation control bits, the converter updates its channel selection (internal or external SCK and free-running conversion immediately and is valid for the next conversion. The details modes). These various modes do not require programming of channel selection control bits are described in the Input configuration registers; moreover, they do not disturb the Data Mode section. The output data is shifted out the SDO cyclic operation described above. These modes of opera- pin under the control of the serial clock (SCK). The output tion are described in detail in the Serial Interface Timing data is updated on the falling edge of SCK allowing the Modes section. CS BIT18 BIT17 BIT16 BIT15 BIT14 BIT13 BIT12 BIT11 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 SDO EOC (0) SIG MSB B22 LSB Hi-Z CONVERSON RESULT SCK SDI ODD/ (1) (0) EN SGL A2 A1 A0 DON’T CARE SIGN SLEEP DATA INPUT/OUTPUT CONVERSION 24391 F03a
Figure 3a. Input/Output Data Timing
CONVERSION RESULT CONVERSION RESULT CONVERSION RESULT N – 1 N N + 1 SDO Hi-Z Hi-Z Hi-Z SCK SDI DON’T CARE DON’T CARE ADDRESS ADDRESS ADDRESS N N + 1 N + 2 OUTPUT OUTPUT OUTPUT OPERATION N – 1 CONVERSION N N CONVERSION N + 1 N + 1 24391 F03b
Figure 3b. Typical Operation Sequence
24391fb 8 For more information www.linear.com/LTC2439-1 Document Outline Features Applications Typical Application Absolute Maximum Ratings Order Information Electrical Characteristics Converter Characteristics Analog Input and Reference Digital Inputs and Digital Outputs POWER REQUIREMENTS Timing Characteristics Pin Functions FUNCTIONAL Block Diagram Test CircuitS Applications Information Package Description Revision History Typical Application Related Parts
