Datasheet LTC2508-32 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 32-Bit Over-Sampling ADC with Configurable Digital Filter |
| Pages / Page | 36 / 5 — POWER REQUIREMENTS. The. denotes the specifications which apply over the … |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
POWER REQUIREMENTS. The. denotes the specifications which apply over the full operating temperature
Model Line for this Datasheet
Text Version of Document
LTC2508-32
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l 2.375 2.5 2.625 V OVDD Supply Voltage l 1.71 5.25 V IVDD Supply Current 1Msps Sample Rate l 9.5 13 mA IOVDD Supply Current 1Msps Sample Rate (CL = 20pF) 1 mA IPD Power Down Mode Conversion Done (IVDD + IOVDD + IREF) l 6 350 µA PD Power Dissipation 1Msps Sample Rate (IVDD) 24 32.5 mW Power Down Mode Conversion Done (IVDD + IOVDD + IREF) 15 875 µW
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l 1 Msps fDRA Output Data Rate at SDOA l 3.9 ksps fDRB Output Data Rate at SDOB l 1 Msps tCONV Conversion Time l 578 652 ns tACQ Acquisition Time tACQ = tCYC – tCONV – tBUSYLH (Note 8) l 335 ns tCYC Time Between Conversions l 1000 ns tMCLKH MCLK High Time l 20 ns tMCLKL Minimum Low Time for MCLK (Note 12) l 20 ns tBUSYLH MCLK↑ to BUSY↑ Delay CL = 20pF l 13 ns tDRLLH MCLK to DRL↑ Delay CL = 20pF l 18 ns tQUIET SCKA, SCKB Quiet Time from MCLK↑ (Note 8) l 10 ns tSCKA SCKA Period (Notes 12, 13) l 10 ns tSCKAH SCKA High Time l 4 ns tSCKAL SCKA Low Time l 4 ns tDSDOA SDOA Data Valid Delay from SCKA↑ CL = 20pF, OVDD = 5.25V l 8.5 ns CL = 20pF, OVDD = 2.5V l 8.5 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDOA SDOA Data Remains Valid Delay from SCKA↑ CL = 20pF (Note 8) l 1 ns tDSDOADRLL SDOA Data Valid Delay from DRL↓ CL = 20pF (Note 8) l 5 ns tENAA Bus Enable Time After RDLA↓ (Note 12) l 16 ns tDISA Bus Relinquish Time After RDLA↑ (Note 12) l 13 ns tSCKB SCKB Period (Notes 12, 13) l 10 ns tSCKBH SCKB High Time l 4 ns tSCKBL SCKB Low Time l 4 ns tDSDOB SDOB Data Valid Delay from SCKB↑ CL = 20pF, OVDD = 5.25V l 8.5 ns CL = 20pF, OVDD = 2.5V l 8.5 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDOB SDOB Data Remains Valid Delay from SCKB↑ CL = 20pF (Note 8) l 1 ns 250832fc For more information www.linear.com/LTC2508-32 5
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l 2.375 2.5 2.625 V OVDD Supply Voltage l 1.71 5.25 V IVDD Supply Current 1Msps Sample Rate l 9.5 13 mA IOVDD Supply Current 1Msps Sample Rate (CL = 20pF) 1 mA IPD Power Down Mode Conversion Done (IVDD + IOVDD + IREF) l 6 350 µA PD Power Dissipation 1Msps Sample Rate (IVDD) 24 32.5 mW Power Down Mode Conversion Done (IVDD + IOVDD + IREF) 15 875 µW
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l 1 Msps fDRA Output Data Rate at SDOA l 3.9 ksps fDRB Output Data Rate at SDOB l 1 Msps tCONV Conversion Time l 578 652 ns tACQ Acquisition Time tACQ = tCYC – tCONV – tBUSYLH (Note 8) l 335 ns tCYC Time Between Conversions l 1000 ns tMCLKH MCLK High Time l 20 ns tMCLKL Minimum Low Time for MCLK (Note 12) l 20 ns tBUSYLH MCLK↑ to BUSY↑ Delay CL = 20pF l 13 ns tDRLLH MCLK to DRL↑ Delay CL = 20pF l 18 ns tQUIET SCKA, SCKB Quiet Time from MCLK↑ (Note 8) l 10 ns tSCKA SCKA Period (Notes 12, 13) l 10 ns tSCKAH SCKA High Time l 4 ns tSCKAL SCKA Low Time l 4 ns tDSDOA SDOA Data Valid Delay from SCKA↑ CL = 20pF, OVDD = 5.25V l 8.5 ns CL = 20pF, OVDD = 2.5V l 8.5 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDOA SDOA Data Remains Valid Delay from SCKA↑ CL = 20pF (Note 8) l 1 ns tDSDOADRLL SDOA Data Valid Delay from DRL↓ CL = 20pF (Note 8) l 5 ns tENAA Bus Enable Time After RDLA↓ (Note 12) l 16 ns tDISA Bus Relinquish Time After RDLA↑ (Note 12) l 13 ns tSCKB SCKB Period (Notes 12, 13) l 10 ns tSCKBH SCKB High Time l 4 ns tSCKBL SCKB Low Time l 4 ns tDSDOB SDOB Data Valid Delay from SCKB↑ CL = 20pF, OVDD = 5.25V l 8.5 ns CL = 20pF, OVDD = 2.5V l 8.5 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDOB SDOB Data Remains Valid Delay from SCKB↑ CL = 20pF (Note 8) l 1 ns 250832fc For more information www.linear.com/LTC2508-32 5
