Datasheet LTC2508-32 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 32-Bit Over-Sampling ADC with Configurable Digital Filter |
| Pages / Page | 36 / 6 — ADC TIMING CHARACTERISTICS. The. denotes the specifications which apply … |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
ADC TIMING CHARACTERISTICS. The. denotes the specifications which apply over the full operating
Model Line for this Datasheet
Text Version of Document
LTC2508-32
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tDSDOBBUSYL SDOB Data Valid Delay from BUSY↓ CL = 20pF (Note 8) l 5 ns tENB Bus Enable Time After RDLB↓ (Note 12) l 16 ns tDISB Bus Relinquish Time After RDLB↑ (Note 12) l 13 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve. Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band. reliability and lifetime.
Note 8:
Guaranteed by design, not subject to test.
Note 2:
All voltage values are with respect to ground.
Note 9:
Bipolar zero-scale error is the offset voltage measured from
Note 3:
When these pin voltages are taken below ground or above REF or –0.5LSB when the output code flickers between 0000 0000 0000 0000 OVDD, they will be clamped by internal diodes. This product can handle 0000 0000 0000 0000 and 1111 1111 1111 1111 1111 1111 1111 input currents up to 100mA below ground or above REF or OVDD without 1111. Full-scale bipolar error is the worst-case of –FS or +FS untrimmed latch-up. deviation from ideal first and last code transitions and includes the effect
Note 4:
V of offset error. DD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 1MHz, DF = 256.
Note 10:
All specifications in dB are referred to a full-scale ±5V input with
Note 5:
Recommended operating conditions. a 5V reference voltage.
Note 6:
Transition noise is defined as the noise level of the ADC with IN+
Note 11:
fSMPL = 1MHz, IREF varies proportionally with sample rate. and IN– shorted.
Note 12:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V and OVDD = 5.25V.
Note 13:
tSCKA, tSCKB of 10ns maximum allows a shift clock frequency up to 100MHz for rising edge capture. 0.8•OVDD tWIDTH 0.2•OVDD t t 50% 50% DELAY DELAY 250832 F01 0.8•OVDD 0.8•OVDD 0.2•OVDD 0.2•OVDD
Figure 1. Voltage Levels for Specifications
250832fc 6 For more information www.linear.com/LTC2508-32
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tDSDOBBUSYL SDOB Data Valid Delay from BUSY↓ CL = 20pF (Note 8) l 5 ns tENB Bus Enable Time After RDLB↓ (Note 12) l 16 ns tDISB Bus Relinquish Time After RDLB↑ (Note 12) l 13 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve. Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band. reliability and lifetime.
Note 8:
Guaranteed by design, not subject to test.
Note 2:
All voltage values are with respect to ground.
Note 9:
Bipolar zero-scale error is the offset voltage measured from
Note 3:
When these pin voltages are taken below ground or above REF or –0.5LSB when the output code flickers between 0000 0000 0000 0000 OVDD, they will be clamped by internal diodes. This product can handle 0000 0000 0000 0000 and 1111 1111 1111 1111 1111 1111 1111 input currents up to 100mA below ground or above REF or OVDD without 1111. Full-scale bipolar error is the worst-case of –FS or +FS untrimmed latch-up. deviation from ideal first and last code transitions and includes the effect
Note 4:
V of offset error. DD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 1MHz, DF = 256.
Note 10:
All specifications in dB are referred to a full-scale ±5V input with
Note 5:
Recommended operating conditions. a 5V reference voltage.
Note 6:
Transition noise is defined as the noise level of the ADC with IN+
Note 11:
fSMPL = 1MHz, IREF varies proportionally with sample rate. and IN– shorted.
Note 12:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V and OVDD = 5.25V.
Note 13:
tSCKA, tSCKB of 10ns maximum allows a shift clock frequency up to 100MHz for rising edge capture. 0.8•OVDD tWIDTH 0.2•OVDD t t 50% 50% DELAY DELAY 250832 F01 0.8•OVDD 0.8•OVDD 0.2•OVDD 0.2•OVDD
Figure 1. Voltage Levels for Specifications
250832fc 6 For more information www.linear.com/LTC2508-32
