Datasheet LTC1380, LTC1393 (Analog Devices) - 8

LTC1380/LTC1393
W U W TI I G DIAGRA
ADDRESS BYTE COMMAND BYTE t t HIGH r tf S S P SCL t t t HD:STA LOW SU:DAT t t HD:DAT SU:STA tSU:STO SDA FROM 1 0 0 1 * A1 A0 0 X X X X EN C2 C1 C0 HOST tBUF *0 FOR LTC1380, 1 FOR LTC1393 SDA FROM t LTC1380/LTC1393 OFF tON tOPEN DO
U U W U APPLICATIONS INFORMATION Theory of Operation
A send byte protocol is initiated by the SMBus host with a start bit followed by a 7-bit address code and a write bit. The LTC1380/LTC1393 are analog input multiplexers with Each slave compares the address code with its address. an SMBus digital interface. The LTC1380 is a single-ended The send byte write bit is Low. The selected slaves then 8-to-1 multiplexer; the LTC1393 is a differential 4-to-1 reply with an acknowledge bit by pulling the SDA line Low. mulitplexer. The LTC1380 operates on either bipolar or Next, the host sends an 8-bit command byte. When the unipolar supplies, the LTC1393 operates on a single selected slave receives the whole command byte, it ac- supply. The minimum VCC supply for the LTC1380/LTC1393 knowledges and retains the command byte in the shift is 2.7V. The maximum supply voltage (VCC to VEE for the register. The host can terminate the serial transfer with a LTC1380, VCC for the LTC1393) should not exceed 14V. stop bit or communicate with another slave device with a The multiplexer switches operate within the entire power repeat start. When a repeat start occurs but the slave is not supply range. The LTC1380 VCC and VEE supplies can be selected, the command byte data is kept in the shift offset such as 2.7V/–11V and 11V/– 3V. register but the multiplexer control is not updated. The
Serial Interface
multiplexer control latches the new command from the shift register on the first stop bit after a successful com- The LTC1380/LTC1393 serial interface supports SMBus mand byte transfer. This allows the host to synchronize send byte protocol as shown below with two interface several slave devices with a single stop bit. A1 and A0 signals, SCL and SDA. select one of the four possible LTC1380/LTC1393 ad- dresses as shown in Table 1. This allows up to four similar
LTC1380 Send Byte Protocol
devices to share the same SMBus, expanding the multi- S 1 0 0 1 0 A1 A0 W A X X X X EN C2 C1 C0 A P plexer to 32 single-ended channels with the LTC1380; 16
LTC1393 Send Byte Protocol
differential channels with the LTC1393. The first stop bit S 1 0 0 1 1 A1 A0 W A X X X X EN C2 C1 C0 A P after a successful send byte transfer will latch in the ADDRESS BYTE COMMAND BYTE multiplexer control bits (EN, C2, C1 and C0) and initiate a S = SMBus START BIT break-before-make sequence. P = SMBus STOP BIT (THE FIRST STOP BIT AFTER A SUCCESSFUL COMMAND BYTE UPDATES THE MULTIPLEXER CONTROL LATCH) A = ACKNOWLEDGE BIT FROM LTC1380/LTC1393 W = WRITE COMMAND BIT A1, A0 = ADDRESS BITS EN, C2, C1, C0 = MULTIPLEXER CONTROL BITS 8