Datasheet LT3582, LT3582-5, LT3582-12 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Boost and Single Inductor Inverting DC/DC Converters with Optional I2C Programing and OTP |
| Pages / Page | 28 / 8 — PIN FUNCTIONS. CA (Pin 1):. CAPP (Pins 10, 11):. VOUTN (Pin 2):. SWP (Pin … |
| File Format / Size | PDF / 328 Kb |
| Document Language | English |
PIN FUNCTIONS. CA (Pin 1):. CAPP (Pins 10, 11):. VOUTN (Pin 2):. SWP (Pin 12):. SWN (Pins 3, 4):. GND (Pin 13):. VIN (Pin 5):
Model Line for this Datasheet
Text Version of Document
LT3582/LT3582-5/LT3582-12
PIN FUNCTIONS CA (Pin 1):
I2C Address Select Pin. Tie this pin to VIN to set
CAPP (Pins 10, 11):
Connect the Boost output capacitor the 7-bit address to 0110 001. Tie to GND for 1000 101. from these pins to GND. During shutdown, the voltage on these pins will remain close to the input voltage due to
VOUTN (Pin 2):
Negative Output Voltage Pin. When the con- the path through the Boost inductor and Schottky. During verter is operating, this pin is regulated to the programmed normal operation, CAPP will be boosted slightly higher negative output voltage. Place a ceramic capacitor from than the programmed output voltage. this pin to GND.
SWP (Pin 12):
Positive Switching Node for the Boost
SWN (Pins 3, 4):
Negative Switching Node for the In- Converter. This is the drain of the internal NMOS power verting Converter. This is the drain of the internal PMOS switch. Connect one end of the Boost inductor to this pin. power switch. Connect one end of the Inverting inductor Keep the trace area on this pin as small as possible. to these pins. Keep the trace area on these pins as small as possible.
GND (Pin 13):
Ground Pin. Tie to a local ground plane. Proper PCB layout is required to achieve advertised per-
VIN (Pin 5):
Input Supply Pin and Source of the PMOS formance; see the Applications Information section for Power Switch. This pin must be bypassed locally with a more information. ceramic capacitor. The operating voltage range of this pin is 2.55V to 5.5V.
VPP (Pin 14):
Programming Voltage Pin. Drive this pin to 13-15V when programming the OTP memory. Float
RAMPN (Pin 6):
Soft-Start Ramp Pin for the Inverting otherwise. A bypass capacitor should be placed from this Converter. Place a capacitor from this pin to GND. A node to GND if V programmable current of 1μA to 8μA (LT3582) or 1μA PP is used for programming. If VPP falls below 13V during OTP programming, an internal FAULT (LT3582-5/LT3582-12) charges this pin during start-up, bit, which can be read through the I2C interface, can be limiting the ramp rate of VOUTN. This pin is discharged to set high. GND during shutdown.
SDA (Pin 15):
I2C Bidirectional Data Pin. Tie to GND or
RAMPP (Pin 7):
Soft-Start Ramp Pin for the Boost Convert- V er. Place a capacitor from this pin to GND. A programmable IN if unused. current of 1μA to 8μA (LT3582) or 1μA (LT3582-5/LT3582-12)
SCL (Pin 16):
I2C Clock Pin. Tie to GND or VIN if un- charges this pin during start-up, limiting the ramp rate of used. VOUTP. This pin is discharged to GND in shutdown.
Exposed Pad (Pin 17):
Ground Pin. Tie to a local ground
SHDN (Pin 8):
Shutdown Pin. Drive this pin to 1.1V or plane. Proper PCB layout is required to achieve advertised higher to enable the part. Drive to 0.3V or lower to shut performance; see the Applications Information section for down. Includes an integrated 222k pull-down resistor. more information.
VOUTP (Pin 9):
Output of the Boost Converter Output Disconnect Circuit. A ceramic capacitor should be placed from this node to GND. During shutdown, this pin is disconnected from the Boost network which allows this pin to discharge to GND, assuming a load is present to discharge the capacitance. 3582512fb 8
PIN FUNCTIONS CA (Pin 1):
I2C Address Select Pin. Tie this pin to VIN to set
CAPP (Pins 10, 11):
Connect the Boost output capacitor the 7-bit address to 0110 001. Tie to GND for 1000 101. from these pins to GND. During shutdown, the voltage on these pins will remain close to the input voltage due to
VOUTN (Pin 2):
Negative Output Voltage Pin. When the con- the path through the Boost inductor and Schottky. During verter is operating, this pin is regulated to the programmed normal operation, CAPP will be boosted slightly higher negative output voltage. Place a ceramic capacitor from than the programmed output voltage. this pin to GND.
SWP (Pin 12):
Positive Switching Node for the Boost
SWN (Pins 3, 4):
Negative Switching Node for the In- Converter. This is the drain of the internal NMOS power verting Converter. This is the drain of the internal PMOS switch. Connect one end of the Boost inductor to this pin. power switch. Connect one end of the Inverting inductor Keep the trace area on this pin as small as possible. to these pins. Keep the trace area on these pins as small as possible.
GND (Pin 13):
Ground Pin. Tie to a local ground plane. Proper PCB layout is required to achieve advertised per-
VIN (Pin 5):
Input Supply Pin and Source of the PMOS formance; see the Applications Information section for Power Switch. This pin must be bypassed locally with a more information. ceramic capacitor. The operating voltage range of this pin is 2.55V to 5.5V.
VPP (Pin 14):
Programming Voltage Pin. Drive this pin to 13-15V when programming the OTP memory. Float
RAMPN (Pin 6):
Soft-Start Ramp Pin for the Inverting otherwise. A bypass capacitor should be placed from this Converter. Place a capacitor from this pin to GND. A node to GND if V programmable current of 1μA to 8μA (LT3582) or 1μA PP is used for programming. If VPP falls below 13V during OTP programming, an internal FAULT (LT3582-5/LT3582-12) charges this pin during start-up, bit, which can be read through the I2C interface, can be limiting the ramp rate of VOUTN. This pin is discharged to set high. GND during shutdown.
SDA (Pin 15):
I2C Bidirectional Data Pin. Tie to GND or
RAMPP (Pin 7):
Soft-Start Ramp Pin for the Boost Convert- V er. Place a capacitor from this pin to GND. A programmable IN if unused. current of 1μA to 8μA (LT3582) or 1μA (LT3582-5/LT3582-12)
SCL (Pin 16):
I2C Clock Pin. Tie to GND or VIN if un- charges this pin during start-up, limiting the ramp rate of used. VOUTP. This pin is discharged to GND in shutdown.
Exposed Pad (Pin 17):
Ground Pin. Tie to a local ground
SHDN (Pin 8):
Shutdown Pin. Drive this pin to 1.1V or plane. Proper PCB layout is required to achieve advertised higher to enable the part. Drive to 0.3V or lower to shut performance; see the Applications Information section for down. Includes an integrated 222k pull-down resistor. more information.
VOUTP (Pin 9):
Output of the Boost Converter Output Disconnect Circuit. A ceramic capacitor should be placed from this node to GND. During shutdown, this pin is disconnected from the Boost network which allows this pin to discharge to GND, assuming a load is present to discharge the capacitance. 3582512fb 8
