Datasheet LT3959 (Analog Devices) - 10

LT3959
applicaTions inForMaTion INTVCC Low Dropout Voltage Regulators Operating Frequency and Synchronization
The LT3959 features two internal low dropout (LDO) volt- The choice of operating frequency may be determined age regulators (VIN LDO and DRIVE LDO) powered from by on-chip power dissipation, otherwise it is a trade-off different supplies (VIN and DRIVE respectively). Both LDO’s between efficiency and component size. Low frequency op- regulate the internal INTVCC supply which powers the gate eration improves efficiency by reducing gate drive current driver and the internal loads, as shown in Figure 1. Both and internal MOSFET and diode switching losses. However, regulators are designed so that current does not flow from lower frequency operation requires a physically larger INTVCC to the LDO input under a reverse bias condition. inductor. Switching frequency also has implications for DRIVE LDO regulates the INTVCC to 4.75V, while VIN LDO loop compensation. The LT3959 uses a constant-frequency regulates the INTVCC to 3.75V. VIN LDO is turned off when architecture that can be programmed over a 100kHz to the INTVCC voltage is greater than 3.75V (typical). Both 1MHz range with a single external resistor from the RT LDO’s can be turned off if the INTVCC pin is driven by a pin to SGND, as shown in Figure 1. The RT pin must have supply of 4.75V or higher but less than 8V (the INTVCC an external resistor to SGND for proper operation of the maximum voltage rating is 8V). A table of the LDO sup- LT3959. A table for selecting the value of RT for a given ply and output voltage combination is shown in Table 1. operating frequency is shown in Table 2.
Table 1. LDO’s Supply and Output Voltage Combination (Assuming Table 2. Timing Resistor (RT) Value That the LDO Dropout Voltage is 0.15V) OSCILLATOR FREQUENCY (kHz) RT (kΩ) SUPPLY VOLTAGES LDO OUTPUT LDO STATUS
100 86.6
V (Note 7) IN DRIVE INTVCC
200 41.2 VIN ≤ 3.9V VDRIVE < VIN VIN – 0.15V #1 Is ON 300 27.4 VDRIVE = VIN VIN – 0.15V #1 #2 are ON 400 21.0 VIN < VDRIVE < 4.9V VDRIVE – 0.15V #2 Is ON 500 16.5 4.9V ≤ VDRIVE ≤ 40V 4.75V #2 Is ON 600 13.7 3.9V < VIN ≤ 40V VDRIVE < 3.9V 3.75V #1 Is ON 700 11.5 VDRIVE = 3.9V 3.75V #1 #2 are ON 800 9.76 3.9V < VDRIVE < 4.9V VDRIVE – 0.15V #2 Is ON 900 8.45 4.9V ≤ VDRIVE ≤ 40V 4.75V #2 Is ON 1000 6.81
Note 7:
#1 is VIN LDO and #2 is DRIVE LDO The switching frequency of the LT3959 can be synchro- nized to the positive edge of an external clock source. The DRIVE pin provides flexibility to power the gate driver By providing a digital clock signal into the SYNC pin, and the internal loads from a supply that is available only the LT3959 will operate at the SYNC clock frequency. If when the switcher is enabled and running. If not used, this feature is used, an R the DRIVE pin should be tied to V T resistor should be chosen to IN. program a switching frequency 20% slower than SYNC The INTVCC pin must be bypassed to SGND immediately pulse frequency. The SYNC pulse should have a minimum adjacent to the INTVCC pin with a minimum of 4.7µF ceramic pulse width of 200ns. Tie the SYNC pin to SGND if this capacitor. Good bypassing is necessary to supply the high feature is not used. transient currents required by the MOSFET gate driver. 3959fa 10 For more information www.linear.com/LT3959 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts