Datasheet LT8710 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Synchronous SEPIC/Inverting/Boost Controller with Output Current Control |
| Pages / Page | 44 / 9 — pin FuncTions FBX (Pin 1):. ISN, ISP (Pins 6, 7):. C (Pin 2):. SS (Pin … |
| File Format / Size | PDF / 657 Kb |
| Document Language | English |
pin FuncTions FBX (Pin 1):. ISN, ISP (Pins 6, 7):. C (Pin 2):. SS (Pin 3):. BIAS (Pin 8):. INTVEE (Pin 9):. FLAG (Pin 4):
Model Line for this Datasheet
Text Version of Document
LT8710
pin FuncTions FBX (Pin 1):
Positive and Negative Feedback Pin. For a value is 10nF to 100nF. A 51.8mV offset is added to the boost, SEPIC, or inverting converter, tie a resistor from amplifier, so when the average ISP – ISN voltage is 0V, the FBX pin to VOUT according to the following equations: the IMON voltage is 616mV. When the average voltage V across the ISP and ISN pins is 50mV, the IMON pin will R OUT – 1.213V FBX = ; Boost or SEPIC Converter output 1.213V. Do not resistively load down this pin. 83.7µA |V
ISN, ISP (Pins 6, 7):
Output Current Sense Negative and R OUT |+ 9.6mV FBX = ; Inverting Converter Positive Input Pins Respectively. Kelvin connect ISN and 83.1µA ISP pins to a sense resistor to limit the output current. The
V
commanded NFET current will limit the voltage difference
C (Pin 2):
Error Amplifier Output Pin. Tie external com- pensation network to this pin. across the sense resistor to 50mV.
SS (Pin 3):
Soft-Start Pin. Place a soft-start capacitor here
BIAS (Pin 8):
Alternate Input Supply and PFET Bias Pin. that is greater than 5x the IMON capacitor. Upon start-up, Must be locally bypassed. The BIAS pin sets the top rail for the SS pin will be charged by a (nominally) 260k resistor the TG gate driver. Must connect to the converter’s VOUT to ~2.7V. During a current overload as seen by ISP - ISN, for a positive output voltage or INTVCC for a converter’s overtemperature, or UVLO condition, the SS pin will be negative output voltage. quickly discharged to reset the part. Once those conditions
INTVEE (Pin 9):
6.18V-Below-BIAS Regulator Pin. Must are clear, the part will attempt to restart. be local y bypassed with a minimum capacitance of
FLAG (Pin 4):
Power Good or C/10 Indication Pin. The 2.2µF to BIAS. This pin sets the bottom rail for the TG FLAG pin functions as an active high power good pin if gate driver. The TG gate driver can begin switching when C/10 is true. Alternatively, the FLAG pin functions as an BIAS – INTVEE exceeds 3.42V (typical). Connect pin to active high C/10 indication pin if power is good. Power ground for an inverting converter. is good when FBX < 68.5mV or FBX > 1.153V and has
TG (Pin 10):
PFET Gate Drive Pin. Low and high levels are 58mV of hysteresis. When FBX = 1.153V, it’s 5% below BIAS – INTVEE and BIAS respectively. regulation which corresponds to ~10% below regulation on V
BG (Pin 11):
NFET Gate Drive Pin. Low and high levels OUT (for VOUT > 8V). Active high C/10 indication is when the charge current seen by the ISP and ISN pins is are GND and INTVCC respectively. less than 10% of full current (VISP – VISN < 5mV) as the
INTVCC (Pin 12):
6.3V Dual Input LDO Regulator Pin. Must charge current decreases. For increasing charge currents, be locally bypassed with a minimum capacitance of 2.2µF the C/10 threshold has to reach 20% of full current (VISP to GND. Logic will choose to run INTVCC from the VIN or – VISN > 10mV). The C/10 indication can be used to set BIAS pins. A maximum 5mA external load can connect the bulk and float voltage when charging a battery. For to the INTVCC pin. The undervoltage lockout on INTVCC is either C/10 or power good indicators, there is a 100µs 4V (typical). The BG gate driver can begin switching when anti-glitch delay. A pull-up resistor or some other form INTVCC exceeds 4V (typical). of pull-up network needs to exist on this pin to use these features. See the Block Diagram and Applications section
VIN (Pin 13):
Input Supply Pin. Must be locally bypassed. for more information. Can run down to 0V as long as BIAS > 4.5V.
IMON (Pin 5):
Output Current Sense Monitor Output Pin.
CSN, CSP (Pins 14, 15):
NFET Current Sense Negative Outputs a voltage that is proportional to the voltage seen and Positive Input Pins Respectively. Kelvin connect these across the ISP and ISN pins. pins to a sense resistor to limit the NFET switch current. The maximum sense voltage at low duty cycle is 50mV. VIMON = 11.9 • (VISP – ISN + 51.8mV)
EN/FBIN (Pin 16):
Enable and Input Voltage Regulation Since the voltage across the ISP and ISN pins is AC, a Pin. In conjunction with the UVLO (undervoltage lockout) filtering capacitor is needed on the IMON pin to average circuit, this pin is used to enable/disable the chip and out the ISP and ISN voltage. Recommended capacitor restart the soft-start sequence. The EN/FBIN pin is also 8710f For more information www.linear.com/LT8710 9
pin FuncTions FBX (Pin 1):
Positive and Negative Feedback Pin. For a value is 10nF to 100nF. A 51.8mV offset is added to the boost, SEPIC, or inverting converter, tie a resistor from amplifier, so when the average ISP – ISN voltage is 0V, the FBX pin to VOUT according to the following equations: the IMON voltage is 616mV. When the average voltage V across the ISP and ISN pins is 50mV, the IMON pin will R OUT – 1.213V FBX = ; Boost or SEPIC Converter output 1.213V. Do not resistively load down this pin. 83.7µA |V
ISN, ISP (Pins 6, 7):
Output Current Sense Negative and R OUT |+ 9.6mV FBX = ; Inverting Converter Positive Input Pins Respectively. Kelvin connect ISN and 83.1µA ISP pins to a sense resistor to limit the output current. The
V
commanded NFET current will limit the voltage difference
C (Pin 2):
Error Amplifier Output Pin. Tie external com- pensation network to this pin. across the sense resistor to 50mV.
SS (Pin 3):
Soft-Start Pin. Place a soft-start capacitor here
BIAS (Pin 8):
Alternate Input Supply and PFET Bias Pin. that is greater than 5x the IMON capacitor. Upon start-up, Must be locally bypassed. The BIAS pin sets the top rail for the SS pin will be charged by a (nominally) 260k resistor the TG gate driver. Must connect to the converter’s VOUT to ~2.7V. During a current overload as seen by ISP - ISN, for a positive output voltage or INTVCC for a converter’s overtemperature, or UVLO condition, the SS pin will be negative output voltage. quickly discharged to reset the part. Once those conditions
INTVEE (Pin 9):
6.18V-Below-BIAS Regulator Pin. Must are clear, the part will attempt to restart. be local y bypassed with a minimum capacitance of
FLAG (Pin 4):
Power Good or C/10 Indication Pin. The 2.2µF to BIAS. This pin sets the bottom rail for the TG FLAG pin functions as an active high power good pin if gate driver. The TG gate driver can begin switching when C/10 is true. Alternatively, the FLAG pin functions as an BIAS – INTVEE exceeds 3.42V (typical). Connect pin to active high C/10 indication pin if power is good. Power ground for an inverting converter. is good when FBX < 68.5mV or FBX > 1.153V and has
TG (Pin 10):
PFET Gate Drive Pin. Low and high levels are 58mV of hysteresis. When FBX = 1.153V, it’s 5% below BIAS – INTVEE and BIAS respectively. regulation which corresponds to ~10% below regulation on V
BG (Pin 11):
NFET Gate Drive Pin. Low and high levels OUT (for VOUT > 8V). Active high C/10 indication is when the charge current seen by the ISP and ISN pins is are GND and INTVCC respectively. less than 10% of full current (VISP – VISN < 5mV) as the
INTVCC (Pin 12):
6.3V Dual Input LDO Regulator Pin. Must charge current decreases. For increasing charge currents, be locally bypassed with a minimum capacitance of 2.2µF the C/10 threshold has to reach 20% of full current (VISP to GND. Logic will choose to run INTVCC from the VIN or – VISN > 10mV). The C/10 indication can be used to set BIAS pins. A maximum 5mA external load can connect the bulk and float voltage when charging a battery. For to the INTVCC pin. The undervoltage lockout on INTVCC is either C/10 or power good indicators, there is a 100µs 4V (typical). The BG gate driver can begin switching when anti-glitch delay. A pull-up resistor or some other form INTVCC exceeds 4V (typical). of pull-up network needs to exist on this pin to use these features. See the Block Diagram and Applications section
VIN (Pin 13):
Input Supply Pin. Must be locally bypassed. for more information. Can run down to 0V as long as BIAS > 4.5V.
IMON (Pin 5):
Output Current Sense Monitor Output Pin.
CSN, CSP (Pins 14, 15):
NFET Current Sense Negative Outputs a voltage that is proportional to the voltage seen and Positive Input Pins Respectively. Kelvin connect these across the ISP and ISN pins. pins to a sense resistor to limit the NFET switch current. The maximum sense voltage at low duty cycle is 50mV. VIMON = 11.9 • (VISP – ISN + 51.8mV)
EN/FBIN (Pin 16):
Enable and Input Voltage Regulation Since the voltage across the ISP and ISN pins is AC, a Pin. In conjunction with the UVLO (undervoltage lockout) filtering capacitor is needed on the IMON pin to average circuit, this pin is used to enable/disable the chip and out the ISP and ISN voltage. Recommended capacitor restart the soft-start sequence. The EN/FBIN pin is also 8710f For more information www.linear.com/LT8710 9
