Datasheet LTC1771 (Analog Devices) - 10

LTC1771
U U W U APPLICATIO S I FOR ATIO
continuous mode, IGATECHG = fQP where QP is the gate To minimize no-load supply current, resistor values in the charge of the internal switch. Both the DC bias and gate megohm range should be used. The increase in supply charge losses are proportional to VIN and thus their current due to the feedback resistors can be calculated effects will be more pronounced at higher supply from: voltages. V  V  OUT OUT 3. I2R losses are predicted from the internal switch, induc- ∆IVIN = R1+R2 VIN  tor and current sense resistor. In continuous mode the average output current flows through L but is “chopped” A 5pF feedforward capacitor across R2 is recommended between the P-channel MOSFET in series with RSENSE to minimize output voltage ripple in Burst Mode operation. and the output diode. The MOSFET RDS(ON) plus RSENSE multiplied by the duty cycle can be summed with the
Run/Soft-Start Function
resistance of L to obtain I2R losses. The RUN/SS pin is a dual purpose pin that provides the 4. The catch diode loss is proportional to the forward drop soft- start function and a means to shut down the LTC1771. as the diode conducts current during the off-time and is Soft-start reduces the input surge current from VIN by more pronounced at high supply voltages where the gradually increasing the internal current limit. Power off-time is long. However, as discussed in the Catch supply sequencing can also be accomplished using Diode section, diodes with lower forward drops often this pin. have higher leakage currents, so although efficiency is An internal 1µA current source charges up an external improved, the no-load supply current will increase. The capacitor C diode loss is calculated by multiplying the forward SS. When the voltage on the RUN/SS reaches 1V, the LTC1771 begins operating. As the voltage on the voltage drop times the diode duty cycle multiplied by RUN/SS continues to ramp from 1V to 2.2V, the internal the load current. current limit is also ramped at a proportional linear rate. Other losses including CIN and COUT ESR dissipative The current limits begins near 40% maximum load at losses, and inductor core losses, generally account for VRUN/SS = 1V and ends at maximum load at VRUN/SS = less than 2% total additional loss. 2.2V. The output current thus ramps up slowly, reducing the starting surge current required from the input power
Output Voltage Programming
supply. If the RUN/SS has been pulled all the way to The output voltage is programmed with an external divider ground, there will be a delay before the current limit starts from V increasing and is given by: OUT to VFB (Pin 1) as shown in Figure 2. The regulated voltage is determined by: tDELAY ≈ CSS/ICHG  R2 where ICHG ≅ 1µA. Pulling the RUN/SS pin below 0.5V VOUT = 1 2 . 3 1+  R  1 puts the LTC1771 into a low quiescent current shutdown (IQ < 2µA). VOUT
Foldback Current Limiting
As described in the Catch Diode Selection, the worst-case C R2 FF 5pF dissipation for diode occurs with a short-circuit output, VFB when the diode conducts the current limit value almost LTC1771 R1 continuously. In most applications this will not cause GND excessive heating, even for extended fault intervals. How- 1771 F02 ever, when heat sinking is at a premium or higher forward voltage drop diodes are being used, foldback current
Figure 2. LTC1771 Adjustable Configuaration
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