Datasheet AD7779 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 8-Channel, 24-Bit, Simultaneous Sampling ADC |
| Pages / Page | 101 / 4 — Data Sheet. AD7779 |
| Revision | C |
| File Format / Size | PDF / 1.8 Mb |
| Document Language | English |
Data Sheet. AD7779
Model Line for this Datasheet
Text Version of Document
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Data Sheet AD7779
Channel 1 Offset Upper Byte Register ... 78 Channel 6 Gain Lower Byte Register ... 86 Channel 1 Offset Middle Byte Register .. 78 Channel 7 Offset Upper Byte Register ... 87 Channel 1 Offset Lower Byte Register ... 78 Channel 7 Offset Middle Byte Register .. 87 Channel 1 Gain Upper Byte Register.. 78 Channel 7 Offset Lower Byte Register ... 87 Channel 1 Gain Middle Byte Register .. 79 Channel 7 Gain Upper Byte Register ... 87 Channel 1 Gain Lower Byte Register .. 79 Channel 7 Gain Middle Byte Register .. 88 Channel 2 Offset Upper Byte Register ... 79 Channel 7 Gain Lower Byte Register ... 88 Channel 2 Offset Middle Byte Register .. 79 Channel 0 Status Register .. 88 Channel 2 Offset Lower Byte Register ... 80 Channel 1 Status Register .. 89 Channel 2 Gain Upper Byte Register.. 80 Channel 2 Status Register .. 89 Channel 2 Gain Middle Byte Register .. 80 Channel 3 Status Register .. 90 Channel 2 Gain Lower Byte Register .. 80 Channel 4 Status Register .. 90 Channel 3 Offset Upper Byte Register ... 81 Channel 5 Status Register .. 91 Channel 3 Offset Middle Byte Register .. 81 Channel 6 Status Register .. 91 Channel 3 Offset Lower Byte Register ... 81 Channel 7 Status Register .. 92 Channel 3 Gain Upper Byte Register.. 81 Channel 0/Channel 1 DSP Errors Register.. 92 Channel 3 Gain Middle Byte Register .. 82 Channel 2/Channel 3 DSP Errors Register.. 93 Channel 3 Gain Lower Byte Register .. 82 Channel 4/Channel 5 DSP Errors Register.. 93 Channel 4 Offset Upper Byte Register ... 82 Channel 6/Channel 7 DSP Errors Register.. 94 Channel 4 Offset Middle Byte Register .. 82 Channel 0 to Channel 7 Error Register Enable Register ... 94 Channel 4 Offset Lower Byte Register ... 83 General Errors Register 1 ... 95 Channel 4 Gain Upper Byte Register.. 83 General Errors Register 1 Enable .. 95 Channel 4 Gain Middle Byte Register .. 83 General Errors Register 2 ... 96 Channel 4 Gain Lower Byte Register .. 83 General Errors Register 2 Enable .. 96 Channel 5 Offset Upper Byte Register ... 84 Error Status Register 1 .. 97 Channel 5 Offset Middle Byte Register .. 84 Error Status Register 2 .. 97 Channel 5 Offset Lower Byte Register ... 84 Error Status Register 3 .. 98 Channel 5 Gain Upper Byte Register.. 84 Decimation Rate (N) MSB Register ... 98 Channel 5 Gain Middle Byte Register .. 85 Decimation Rate (N) LSB Register ... 98 Channel 5 Gain Lower Byte Register .. 85 Decimation Rate (IF) MSB Register ... 99 Channel 6 Offset Upper Byte Register ... 85 Decimation Rate (IF) LSB Register .. 99 Channel 6 Offset Middle Byte Register .. 85 SRC Load Source and Load Update Register .. 99 Channel 6 Offset Lower Byte Register ... 86 Outline Dimensions .. 100 Channel 6 Gain Upper Byte Register.. 86 Ordering Guide ... 100 Channel 6 Gain Middle Byte Register .. 86 Rev. B | Page 3 of 100 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DOUTx TIMING CHARACTERISTISTICS SPI TIMING CHARACTERISTISTICS SYNCHRONIZATION PINS AND RESET TIMING CHARACTERISTICS SAR ADC TIMING CHARACTERISTISTICS GPIO SRC UPDATE TIMING CHARACTERISTISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY RMS NOISE AND RESOLUTION HIGH RESOLUTION MODE LOW POWER MODE THEORY OF OPERATION ANALOG INPUTS TRANSFER FUNCTION CORE SIGNAL CHAIN CAPACITIVE PGA INTERNAL REFERENCE AND REFERENCE BUFFERS INTEGRATED LDOs CLOCKING AND SAMPLING DIGITAL RESET AND SYNCHRONIZATION PINS DIGITAL FILTERING SHUTDOWN MODE CONTROLLING THE AD7779 PIN CONTROL MODE SPI CONTROL Functionality Available in SPI Mode Offset and Gain Correction SPI Control Functionality Global Control Functions Per Channel Functions Phase Adjustment PGA Gain Decimation GPIO Pins Σ-∆ Reference Configuration Power Modes LDO Bypassing DIGITAL SPI INTERFACE SPI CRC—Checksum Protection (SPI Control Mode) SPI Read/Write Register Mode (SPI Control Mode) SPI SAR Diagnostic Mode (SPI Control Mode) Σ-∆ Data, ADC Mode SPI Software Reset DIAGNOSTICS AND MONITORING SELF DIAGNOSTICS ERROR General Errors MCLK Switch Error (SPI Control Mode) Reset Detection Internal LDO Status ROM and MEMMAP CRC Σ-∆ ADC Errors Reference Detect (SPI Control Mode) Overvoltage and Undervoltage Events Modulator Saturation Filter Saturation Output Saturation SPI Transmission Errors (SPI Control Mode) CRC Checksum Error SCLK Counter Invalid Read Invalid Write MONITORING USING THE AD7779 SAR ADC(SPI CONTROL MODE) Temperature Sensor Σ-Δ ADC DIAGNOSTICS (SPI CONTROL MODE) Σ-∆ OUTPUT DATA ADC CONVERSION OUTPUT—HEADER AND DATA CRC Header ERROR Header (SPI Control Mode) SAMPLE RATE CONVERTER (SRC) (SPI CONTROL MODE) SRC Bandwidth SRC Group Delay and Latency Settling Time DATA OUTPUT INTERFACE DOUT3 to DOUT0 Data Interface Standalone Mode Daisy-Chain Mode Minimum DCLKx Frequency SPI Interface CALCULATING THE CRC CHECKSUM Σ-∆ CRC Checksum SPI Control Mode Checksum REGISTER SUMMARY REGISTER DETAILS CHANNEL 0 CONFIGURATION REGISTER CHANNEL 1 CONFIGURATION REGISTER CHANNEL 2 CONFIGURATION REGISTER CHANNEL 3 CONFIGURATION REGISTER CHANNEL 4 CONFIGURATION REGISTER CHANNEL 5 CONFIGURATION REGISTER CHANNEL 6 CONFIGURATION REGISTER CHANNEL 7 CONFIGURATION REGISTER DISABLE CLOCKS TO ADC CHANNEL REGISTER CHANNEL 0 SYNC OFFSET REGISTER CHANNEL 1 SYNC OFFSET REGISTER CHANNEL 2 SYNC OFFSET REGISTER CHANNEL 3 SYNC OFFSET REGISTER CHANNEL 4 SYNC OFFSET REGISTER CHANNEL 5 SYNC OFFSET REGISTER CHANNEL 6 SYNC OFFSET REGISTER CHANNEL 7 SYNC OFFSET REGISTER GENERAL USER CONFIGURATION 1 REGISTER GENERAL USER CONFIGURATION 2 REGISTER GENERAL USER CONFIGURATION 3 REGISTER DATA OUTPUT FORMAT REGISTER MAIN ADC METER AND REFERENCE MUX CONTROL REGISTER GLOBAL DIAGNOSTICS MUX REGISTER GPIO CONFIGURATION REGISTER GPIO DATA REGISTER BUFFER CONFIGURATION 1 REGISTER BUFFER CONFIGURATION 2 REGISTER CHANNEL 0 OFFSET UPPER BYTE REGISTER CHANNEL 0 OFFSET MIDDLE BYTE REGISTER CHANNEL 0 OFFSET LOWER BYTE REGISTER CHANNEL 0 GAIN UPPER BYTE REGISTER CHANNEL 0 GAIN MIDDLE BYTE REGISTER CHANNEL 0 GAIN LOWER BYTE REGISTER CHANNEL 1 OFFSET UPPER BYTE REGISTER CHANNEL 1 OFFSET MIDDLE BYTE REGISTER CHANNEL 1 OFFSET LOWER BYTE REGISTER CHANNEL 1 GAIN UPPER BYTE REGISTER CHANNEL 1 GAIN MIDDLE BYTE REGISTER CHANNEL 1 GAIN LOWER BYTE REGISTER CHANNEL 2 OFFSET UPPER BYTE REGISTER CHANNEL 2 OFFSET MIDDLE BYTE REGISTER CHANNEL 2 OFFSET LOWER BYTE REGISTER CHANNEL 2 GAIN UPPER BYTE REGISTER CHANNEL 2 GAIN MIDDLE BYTE REGISTER CHANNEL 2 GAIN LOWER BYTE REGISTER CHANNEL 3 OFFSET UPPER BYTE REGISTER CHANNEL 3 OFFSET MIDDLE BYTE REGISTER CHANNEL 3 OFFSET LOWER BYTE REGISTER CHANNEL 3 GAIN UPPER BYTE REGISTER CHANNEL 3 GAIN MIDDLE BYTE REGISTER CHANNEL 3 GAIN LOWER BYTE REGISTER CHANNEL 4 OFFSET UPPER BYTE REGISTER CHANNEL 4 OFFSET MIDDLE BYTE REGISTER CHANNEL 4 OFFSET LOWER BYTE REGISTER CHANNEL 4 GAIN UPPER BYTE REGISTER CHANNEL 4 GAIN MIDDLE BYTE REGISTER CHANNEL 4 GAIN LOWER BYTE REGISTER CHANNEL 5 OFFSET UPPER BYTE REGISTER CHANNEL 5 OFFSET MIDDLE BYTE REGISTER CHANNEL 5 OFFSET LOWER BYTE REGISTER CHANNEL 5 GAIN UPPER BYTE REGISTER CHANNEL 5 GAIN MIDDLE BYTE REGISTER CHANNEL 5 GAIN LOWER BYTE REGISTER CHANNEL 6 OFFSET UPPER BYTE REGISTER CHANNEL 6 OFFSET MIDDLE BYTE REGISTER CHANNEL 6 OFFSET LOWER BYTE REGISTER CHANNEL 6 GAIN UPPER BYTE REGISTER CHANNEL 6 GAIN MIDDLE BYTE REGISTER CHANNEL 6 GAIN LOWER BYTE REGISTER CHANNEL 7 OFFSET UPPER BYTE REGISTER CHANNEL 7 OFFSET MIDDLE BYTE REGISTER CHANNEL 7 OFFSET LOWER BYTE REGISTER CHANNEL 7 GAIN UPPER BYTE REGISTER CHANNEL 7 GAIN MIDDLE BYTE REGISTER CHANNEL 7 GAIN LOWER BYTE REGISTER CHANNEL 0 STATUS REGISTER CHANNEL 1 STATUS REGISTER CHANNEL 2 STATUS REGISTER CHANNEL 3 STATUS REGISTER CHANNEL 4 STATUS REGISTER CHANNEL 5 STATUS REGISTER CHANNEL 6 STATUS REGISTER CHANNEL 7 STATUS REGISTER CHANNEL 0/CHANNEL 1 DSP ERRORS REGISTER CHANNEL 2/CHANNEL 3 DSP ERRORS REGISTER CHANNEL 4/CHANNEL 5 DSP ERRORS REGISTER CHANNEL 6/CHANNEL 7 DSP ERRORS REGISTER CHANNEL 0 TO CHANNEL 7 ERROR REGISTER ENABLE REGISTER GENERAL ERRORS REGISTER 1 GENERAL ERRORS REGISTER 1 ENABLE GENERAL ERRORS REGISTER 2 GENERAL ERRORS REGISTER 2 ENABLE ERROR STATUS REGISTER 1 ERROR STATUS REGISTER 2 ERROR STATUS REGISTER 3 DECIMATION RATE (N) MSB REGISTER DECIMATION RATE (N) LSB REGISTER DECIMATION RATE (IF) MSB REGISTER DECIMATION RATE (IF) LSB REGISTER SRC LOAD SOURCE AND LOAD UPDATE REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7779
Channel 1 Offset Upper Byte Register ... 78 Channel 6 Gain Lower Byte Register ... 86 Channel 1 Offset Middle Byte Register .. 78 Channel 7 Offset Upper Byte Register ... 87 Channel 1 Offset Lower Byte Register ... 78 Channel 7 Offset Middle Byte Register .. 87 Channel 1 Gain Upper Byte Register.. 78 Channel 7 Offset Lower Byte Register ... 87 Channel 1 Gain Middle Byte Register .. 79 Channel 7 Gain Upper Byte Register ... 87 Channel 1 Gain Lower Byte Register .. 79 Channel 7 Gain Middle Byte Register .. 88 Channel 2 Offset Upper Byte Register ... 79 Channel 7 Gain Lower Byte Register ... 88 Channel 2 Offset Middle Byte Register .. 79 Channel 0 Status Register .. 88 Channel 2 Offset Lower Byte Register ... 80 Channel 1 Status Register .. 89 Channel 2 Gain Upper Byte Register.. 80 Channel 2 Status Register .. 89 Channel 2 Gain Middle Byte Register .. 80 Channel 3 Status Register .. 90 Channel 2 Gain Lower Byte Register .. 80 Channel 4 Status Register .. 90 Channel 3 Offset Upper Byte Register ... 81 Channel 5 Status Register .. 91 Channel 3 Offset Middle Byte Register .. 81 Channel 6 Status Register .. 91 Channel 3 Offset Lower Byte Register ... 81 Channel 7 Status Register .. 92 Channel 3 Gain Upper Byte Register.. 81 Channel 0/Channel 1 DSP Errors Register.. 92 Channel 3 Gain Middle Byte Register .. 82 Channel 2/Channel 3 DSP Errors Register.. 93 Channel 3 Gain Lower Byte Register .. 82 Channel 4/Channel 5 DSP Errors Register.. 93 Channel 4 Offset Upper Byte Register ... 82 Channel 6/Channel 7 DSP Errors Register.. 94 Channel 4 Offset Middle Byte Register .. 82 Channel 0 to Channel 7 Error Register Enable Register ... 94 Channel 4 Offset Lower Byte Register ... 83 General Errors Register 1 ... 95 Channel 4 Gain Upper Byte Register.. 83 General Errors Register 1 Enable .. 95 Channel 4 Gain Middle Byte Register .. 83 General Errors Register 2 ... 96 Channel 4 Gain Lower Byte Register .. 83 General Errors Register 2 Enable .. 96 Channel 5 Offset Upper Byte Register ... 84 Error Status Register 1 .. 97 Channel 5 Offset Middle Byte Register .. 84 Error Status Register 2 .. 97 Channel 5 Offset Lower Byte Register ... 84 Error Status Register 3 .. 98 Channel 5 Gain Upper Byte Register.. 84 Decimation Rate (N) MSB Register ... 98 Channel 5 Gain Middle Byte Register .. 85 Decimation Rate (N) LSB Register ... 98 Channel 5 Gain Lower Byte Register .. 85 Decimation Rate (IF) MSB Register ... 99 Channel 6 Offset Upper Byte Register ... 85 Decimation Rate (IF) LSB Register .. 99 Channel 6 Offset Middle Byte Register .. 85 SRC Load Source and Load Update Register .. 99 Channel 6 Offset Lower Byte Register ... 86 Outline Dimensions .. 100 Channel 6 Gain Upper Byte Register.. 86 Ordering Guide ... 100 Channel 6 Gain Middle Byte Register .. 86 Rev. B | Page 3 of 100 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DOUTx TIMING CHARACTERISTISTICS SPI TIMING CHARACTERISTISTICS SYNCHRONIZATION PINS AND RESET TIMING CHARACTERISTICS SAR ADC TIMING CHARACTERISTISTICS GPIO SRC UPDATE TIMING CHARACTERISTISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY RMS NOISE AND RESOLUTION HIGH RESOLUTION MODE LOW POWER MODE THEORY OF OPERATION ANALOG INPUTS TRANSFER FUNCTION CORE SIGNAL CHAIN CAPACITIVE PGA INTERNAL REFERENCE AND REFERENCE BUFFERS INTEGRATED LDOs CLOCKING AND SAMPLING DIGITAL RESET AND SYNCHRONIZATION PINS DIGITAL FILTERING SHUTDOWN MODE CONTROLLING THE AD7779 PIN CONTROL MODE SPI CONTROL Functionality Available in SPI Mode Offset and Gain Correction SPI Control Functionality Global Control Functions Per Channel Functions Phase Adjustment PGA Gain Decimation GPIO Pins Σ-∆ Reference Configuration Power Modes LDO Bypassing DIGITAL SPI INTERFACE SPI CRC—Checksum Protection (SPI Control Mode) SPI Read/Write Register Mode (SPI Control Mode) SPI SAR Diagnostic Mode (SPI Control Mode) Σ-∆ Data, ADC Mode SPI Software Reset DIAGNOSTICS AND MONITORING SELF DIAGNOSTICS ERROR General Errors MCLK Switch Error (SPI Control Mode) Reset Detection Internal LDO Status ROM and MEMMAP CRC Σ-∆ ADC Errors Reference Detect (SPI Control Mode) Overvoltage and Undervoltage Events Modulator Saturation Filter Saturation Output Saturation SPI Transmission Errors (SPI Control Mode) CRC Checksum Error SCLK Counter Invalid Read Invalid Write MONITORING USING THE AD7779 SAR ADC(SPI CONTROL MODE) Temperature Sensor Σ-Δ ADC DIAGNOSTICS (SPI CONTROL MODE) Σ-∆ OUTPUT DATA ADC CONVERSION OUTPUT—HEADER AND DATA CRC Header ERROR Header (SPI Control Mode) SAMPLE RATE CONVERTER (SRC) (SPI CONTROL MODE) SRC Bandwidth SRC Group Delay and Latency Settling Time DATA OUTPUT INTERFACE DOUT3 to DOUT0 Data Interface Standalone Mode Daisy-Chain Mode Minimum DCLKx Frequency SPI Interface CALCULATING THE CRC CHECKSUM Σ-∆ CRC Checksum SPI Control Mode Checksum REGISTER SUMMARY REGISTER DETAILS CHANNEL 0 CONFIGURATION REGISTER CHANNEL 1 CONFIGURATION REGISTER CHANNEL 2 CONFIGURATION REGISTER CHANNEL 3 CONFIGURATION REGISTER CHANNEL 4 CONFIGURATION REGISTER CHANNEL 5 CONFIGURATION REGISTER CHANNEL 6 CONFIGURATION REGISTER CHANNEL 7 CONFIGURATION REGISTER DISABLE CLOCKS TO ADC CHANNEL REGISTER CHANNEL 0 SYNC OFFSET REGISTER CHANNEL 1 SYNC OFFSET REGISTER CHANNEL 2 SYNC OFFSET REGISTER CHANNEL 3 SYNC OFFSET REGISTER CHANNEL 4 SYNC OFFSET REGISTER CHANNEL 5 SYNC OFFSET REGISTER CHANNEL 6 SYNC OFFSET REGISTER CHANNEL 7 SYNC OFFSET REGISTER GENERAL USER CONFIGURATION 1 REGISTER GENERAL USER CONFIGURATION 2 REGISTER GENERAL USER CONFIGURATION 3 REGISTER DATA OUTPUT FORMAT REGISTER MAIN ADC METER AND REFERENCE MUX CONTROL REGISTER GLOBAL DIAGNOSTICS MUX REGISTER GPIO CONFIGURATION REGISTER GPIO DATA REGISTER BUFFER CONFIGURATION 1 REGISTER BUFFER CONFIGURATION 2 REGISTER CHANNEL 0 OFFSET UPPER BYTE REGISTER CHANNEL 0 OFFSET MIDDLE BYTE REGISTER CHANNEL 0 OFFSET LOWER BYTE REGISTER CHANNEL 0 GAIN UPPER BYTE REGISTER CHANNEL 0 GAIN MIDDLE BYTE REGISTER CHANNEL 0 GAIN LOWER BYTE REGISTER CHANNEL 1 OFFSET UPPER BYTE REGISTER CHANNEL 1 OFFSET MIDDLE BYTE REGISTER CHANNEL 1 OFFSET LOWER BYTE REGISTER CHANNEL 1 GAIN UPPER BYTE REGISTER CHANNEL 1 GAIN MIDDLE BYTE REGISTER CHANNEL 1 GAIN LOWER BYTE REGISTER CHANNEL 2 OFFSET UPPER BYTE REGISTER CHANNEL 2 OFFSET MIDDLE BYTE REGISTER CHANNEL 2 OFFSET LOWER BYTE REGISTER CHANNEL 2 GAIN UPPER BYTE REGISTER CHANNEL 2 GAIN MIDDLE BYTE REGISTER CHANNEL 2 GAIN LOWER BYTE REGISTER CHANNEL 3 OFFSET UPPER BYTE REGISTER CHANNEL 3 OFFSET MIDDLE BYTE REGISTER CHANNEL 3 OFFSET LOWER BYTE REGISTER CHANNEL 3 GAIN UPPER BYTE REGISTER CHANNEL 3 GAIN MIDDLE BYTE REGISTER CHANNEL 3 GAIN LOWER BYTE REGISTER CHANNEL 4 OFFSET UPPER BYTE REGISTER CHANNEL 4 OFFSET MIDDLE BYTE REGISTER CHANNEL 4 OFFSET LOWER BYTE REGISTER CHANNEL 4 GAIN UPPER BYTE REGISTER CHANNEL 4 GAIN MIDDLE BYTE REGISTER CHANNEL 4 GAIN LOWER BYTE REGISTER CHANNEL 5 OFFSET UPPER BYTE REGISTER CHANNEL 5 OFFSET MIDDLE BYTE REGISTER CHANNEL 5 OFFSET LOWER BYTE REGISTER CHANNEL 5 GAIN UPPER BYTE REGISTER CHANNEL 5 GAIN MIDDLE BYTE REGISTER CHANNEL 5 GAIN LOWER BYTE REGISTER CHANNEL 6 OFFSET UPPER BYTE REGISTER CHANNEL 6 OFFSET MIDDLE BYTE REGISTER CHANNEL 6 OFFSET LOWER BYTE REGISTER CHANNEL 6 GAIN UPPER BYTE REGISTER CHANNEL 6 GAIN MIDDLE BYTE REGISTER CHANNEL 6 GAIN LOWER BYTE REGISTER CHANNEL 7 OFFSET UPPER BYTE REGISTER CHANNEL 7 OFFSET MIDDLE BYTE REGISTER CHANNEL 7 OFFSET LOWER BYTE REGISTER CHANNEL 7 GAIN UPPER BYTE REGISTER CHANNEL 7 GAIN MIDDLE BYTE REGISTER CHANNEL 7 GAIN LOWER BYTE REGISTER CHANNEL 0 STATUS REGISTER CHANNEL 1 STATUS REGISTER CHANNEL 2 STATUS REGISTER CHANNEL 3 STATUS REGISTER CHANNEL 4 STATUS REGISTER CHANNEL 5 STATUS REGISTER CHANNEL 6 STATUS REGISTER CHANNEL 7 STATUS REGISTER CHANNEL 0/CHANNEL 1 DSP ERRORS REGISTER CHANNEL 2/CHANNEL 3 DSP ERRORS REGISTER CHANNEL 4/CHANNEL 5 DSP ERRORS REGISTER CHANNEL 6/CHANNEL 7 DSP ERRORS REGISTER CHANNEL 0 TO CHANNEL 7 ERROR REGISTER ENABLE REGISTER GENERAL ERRORS REGISTER 1 GENERAL ERRORS REGISTER 1 ENABLE GENERAL ERRORS REGISTER 2 GENERAL ERRORS REGISTER 2 ENABLE ERROR STATUS REGISTER 1 ERROR STATUS REGISTER 2 ERROR STATUS REGISTER 3 DECIMATION RATE (N) MSB REGISTER DECIMATION RATE (N) LSB REGISTER DECIMATION RATE (IF) MSB REGISTER DECIMATION RATE (IF) LSB REGISTER SRC LOAD SOURCE AND LOAD UPDATE REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
