Datasheet AD7768, AD7768-4 (Analog Devices) - 49

link to page 49 link to page 49 link to page 50 link to page 16 link to page 18 link to page 6
Data Sheet AD7768/AD7768-4 Channel Standby SPI CONTROL
Table 21 and Table 23 show how the user can put channels into The AD7768/AD7768-4 have a 4-wire SPI interface that is standby mode. Set either ST0 or ST1 to Logic 1 to place banks of compatible with QSPI™, MICROWIRE®, and DSPs. The interface four channels into standby mode. When in standby mode, the operates in SPI Mode 0. In SPI Mode 0, SCLK idles low, the channels are disabled but still hold their position in the output falling edge of CS clocks out the MSB, the falling edge of SCLK data stream. The 8-bit header and 24-bit conversion result are is the drive edge, and the rising edge of SCLK is the sample set to all zeros when the ADC channels are set to standby. edge. This means that data is clocked out on the falling/drive The VCM voltage output is associated with the Channel 0 edge and data is clocked in on the rising/sample edge. circuitry. If Channel 0 is put into standby mode, the VCM voltage output is also disabled for maximum power savings. Channel 0 must be enabled while VCM is being used externally
DRIVE EDGE SAMPLE EDGE
to the AD7768/AD7768-4. 080 The crystal excitation circuitry is associated with the Channel 4 14001- (Channel 2 on the AD7768-4) circuitry. If Channel 4 (Channel 2 Figure 78. SPI Mode 0 SCLK Edges on the AD7768-4) is put into standby mode, the crystal circuitry is also disabled for maximum power savings. Channel 4 must be
Accessing the ADC Register Map
enabled while the external crystal is used on the AD7768. To use SPI control mode, set the PIN/SPI pin to logic high. The Channel 2 must be enabled while the external crystal is used on SPI control operates as a 16-bit, 4-wire interface, allowing read the AD7768-4. and write access. Figure 80 shows the interface format between the AD7768/AD7768-4 and the digital host.
Table 21. Truth Table for the AD7768 S T0 and ST1 Pins ST1 ST0 Function
The SPI serial control interface of the AD7768 is an independent 0 0 All channels operational. path for control ing and monitoring the AD7768. There is no 0 1 Channel 0 to Channel 3 in direct link to the data interface. The timing of MCLK and standby. Channel 4 to DCLK is not directly related to the timing of the SPI control Channel 7 operational. interface. However, the user must ensure that the SPI reads and 1 0 Channel 4 to Channel 7 in writes satisfy the minimum t30 specification (see Table 4 and standby. Channel 0 to Table 6) so that the AD7768/AD7768-4 can detect changes to Channel 3 operational. the register map. 1 1 All channels in standby. SPI access is ignored during the period immediately after a
Table 22. Truth Table for the AD7768-4 S T0 Pin
reset. Allow the full ADC start-up time after reset (see Table 1)
ST0 Function
to elapse before accessing the AD7768/AD7768-4 over the SPI 0 All channels operational. interface. 1 Channel 0 to Channel 3 in standby.
Table 23. MODEx Example Selection Mode Hex MODE3 MODE2 MODE1 MODE0 Power Mode DCLK Frequency Data Conversion
0x3 0 0 1 1 Eco MCLK/8 Standard Rev. A | Page 49 of 99 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 1.8 V IOVDD SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA Chip Error Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface FUNCTIONALITY GPIO FUNCTIONALITY AD7768 REGISTER MAP DETAILS (SPI CONTROL) AD7768 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER AD7768-4 REGISTER MAP DETAILS (SPI CONTROL) AD7768-4 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 AND CHANNEL 1 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 2 AND CHANNEL 3 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE