Datasheet AD7172-4 (Analog Devices) - 10

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Data Sheet AD7172-4 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS + – F F O3 8 7 6 5 4 N N N N N RE RE GP AI AI AI AI AI 32 31 30 29 28 27 26 25 AIN0/REF2– 1 24 AIN3 AIN1/REF2+ 2 23 AIN2 DNC 3 22 GPO2 AD7172-4 REGCAPA 4 21 GPIO1 AVSS 5 TOP VIEW 20 GPIO0 (Not to Scale) AVDD1 6 19 REGCAPD AVDD2 7 18 DGND PDSW 8 17 IOVDD 9 10 11 12 13 14 15 16 1 L IO N K R C A K L CS O N /RDY DI R XT CL SC SY 2/ UT ER AL DO T X NOTES 1. DNC = DO NOT CONNECT. 2. SOLDER THE EXPOSED PAD TO A SIMILAR PAD ON THE PCB UNDER THE
02
EXPOSED PAD TO CONFER MECHANICAL STRENGTH TO THE PACKAGE
0 6-
AND FOR HEAT DISSIPATION. THE EXPOSED PAD MUST BE CONNECTED TO
67
AVSS THROUGH THIS PAD ON THE PCB.
12 Figure 4. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1 AIN0/REF2− AI Analog Input 0/Reference 2 Negative Input Terminal. A reference can be applied between the REF2+ and REF2− pins. REF2− can span from AVSS to AVDD1 − 1 V. Analog Input 0 is selectable through the crosspoint multiplexer. Reference 2 can be selected through the REF_SELx bits in the setup configuration (SETUPCONx) registers. 2 AIN1/REF2+ AI Analog Input 1/Reference 2 Positive Input Terminal. A reference can be applied between the REF2+ and REF2− pins. REF2+ can span from AVDD1 to AVSS + 1 V. Analog Input 1 is selectable through the crosspoint multiplexer. Reference 2 can be selected through the REF_SELx bits in the setup configuration (SETUPCONx) registers. 3 DNC Do Not Connect. Do not connect to this pin. 4 REGCAPA AO Analog LDO Regulator Output. Decouple this pin to AVSS using a 1 μF capacitor. 5 AVSS P Negative Analog Supply. This supply ranges from 0 V to −2.75 V and is nominally set to 0 V. 6 AVDD1 P Analog Supply Voltage 1. This voltage ranges from 3.0 V minimum to 5.5 V maximum with respect to AVSS. 7 AVDD2 P Analog Supply Voltage 2. This voltage ranges from 2 V to AVDD1 with respect to AVSS. 8 PDSW AO Power-Down Switch Connected to AVSS. This pin is controlled by the PDSW bit in the GPIOCON register. 9 XTAL1 AI Input 1 for Crystal. 10 XTAL2/CLKIO AI/DI Input 2 for Crystal/Clock Input or Output. See the CLOCKSEL bit settings in the ADCMODE register in Table 28 for more information. 11 DOUT/RDY DO Serial Data Output/Data Ready Output. DOUT/RDY is a dual purpose pin. This pin is a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. The data-word/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY output is tristated. When CS is low, and a register is not being read, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. 12 DIN DI Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register address (RA) bits of the communications register identifying the appropriate register. Data is clocked in on the rising edge of SCLK. 13 SCLK DI Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK pin has a Schmitt triggered input, making the interface suitable for opto-isolated applications. Rev. B | Page 9 of 61 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Recommended Linear Regulators DIGITAL COMMUNICATION Accessing the ADC Register Map AD7172-4 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7172-4 REFERENCE BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE INPUT/OUTPUT EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 7 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE