Datasheet AD9684 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital Converter |
| Pages / Page | 65 / 3 — AD9684. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 5/15—Revision 0: … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
AD9684. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 5/15—Revision 0: Initial Version
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AD9684 Data Sheet TABLE OF CONTENTS
Features .. 1 DDC I/Q Output Selection ... 31 Applications ... 1 DDC General Description .. 31 Functional Block Diagram .. 1 Frequency Translation ... 37 General Description ... 1 General Description ... 37 Revision History ... 2 DDC NCO Plus Mixer Loss and SFDR ... 38 Product Highlights ... 3 Numerically Controlled Oscillator .. 38 Specifications ... 4 FIR Filters .. 40 DC Specifications ... 4 General Description ... 40 AC Specifications .. 5 Half-Band Filters .. 41 Digital Specifications ... 6 DDC Gain Stage ... 42 Switching Specifications .. 7 DDC Complex to Real Conversion Block... 42 Timing Specifications .. 8 DDC Example Configurations ... 43 Absolute Maximum Ratings .. 16 Digital Outputs ... 47 Thermal Characteristics .. 16 Digital Outputs ... 47 ESD Caution .. 16 ADC Overrange .. 47 Pin Configuration and Function Descriptions ... 17 Multichip Synchronization .. 48 Typical Performance Characteristics ... 19 SYNC± Setup and Hold Window Monitor ... 49 Equivalent Circuits ... 22 Test Modes ... 51 Theory of Operation .. 24 ADC Test Modes .. 51 ADC Architecture .. 24 Serial Port Interface (SPI) .. 52 Analog Input Considerations .. 24 Configuration Using the SPI ... 52 Voltage Reference ... 26 Hardware Interface ... 52 Clock Input Considerations .. 27 SPI Accessible Features .. 52 Power-Down/Standby Mode... 28 Memory Map .. 53 Temperature Diode .. 28 Reading the Memory Map Register Table ... 53 ADC Overrange and Fast Detect .. 29 Memory Map Register Table ... 54 ADC Overrange .. 29 Applications Information .. 63 Fast Threshold Detection (FD_A and FD_B) .. 29 Power Supply Recommendations ... 63 Signal Monitor .. 30 Outline Dimensions ... 64 Digital Downconverters (DDCs) .. 31 Ordering Guide .. 64 DDC I/Q Input Selection .. 31
REVISION HISTORY 5/15—Revision 0: Initial Version
Rev. 0 | Page 2 of 64 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjustment Clock Fine Delay Adjustment Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR DIGITAL DOWNCONVERTERS (DDCs) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION BLOCK DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS DIGITAL OUTPUTS Timing Data Clock Output ADC OVERRANGE MULTICHIP SYNCHRONIZATION SYNC± SETUP AND HOLD WINDOW MONITOR TEST MODES ADC TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE
AD9684 Data Sheet TABLE OF CONTENTS
Features .. 1 DDC I/Q Output Selection ... 31 Applications ... 1 DDC General Description .. 31 Functional Block Diagram .. 1 Frequency Translation ... 37 General Description ... 1 General Description ... 37 Revision History ... 2 DDC NCO Plus Mixer Loss and SFDR ... 38 Product Highlights ... 3 Numerically Controlled Oscillator .. 38 Specifications ... 4 FIR Filters .. 40 DC Specifications ... 4 General Description ... 40 AC Specifications .. 5 Half-Band Filters .. 41 Digital Specifications ... 6 DDC Gain Stage ... 42 Switching Specifications .. 7 DDC Complex to Real Conversion Block... 42 Timing Specifications .. 8 DDC Example Configurations ... 43 Absolute Maximum Ratings .. 16 Digital Outputs ... 47 Thermal Characteristics .. 16 Digital Outputs ... 47 ESD Caution .. 16 ADC Overrange .. 47 Pin Configuration and Function Descriptions ... 17 Multichip Synchronization .. 48 Typical Performance Characteristics ... 19 SYNC± Setup and Hold Window Monitor ... 49 Equivalent Circuits ... 22 Test Modes ... 51 Theory of Operation .. 24 ADC Test Modes .. 51 ADC Architecture .. 24 Serial Port Interface (SPI) .. 52 Analog Input Considerations .. 24 Configuration Using the SPI ... 52 Voltage Reference ... 26 Hardware Interface ... 52 Clock Input Considerations .. 27 SPI Accessible Features .. 52 Power-Down/Standby Mode... 28 Memory Map .. 53 Temperature Diode .. 28 Reading the Memory Map Register Table ... 53 ADC Overrange and Fast Detect .. 29 Memory Map Register Table ... 54 ADC Overrange .. 29 Applications Information .. 63 Fast Threshold Detection (FD_A and FD_B) .. 29 Power Supply Recommendations ... 63 Signal Monitor .. 30 Outline Dimensions ... 64 Digital Downconverters (DDCs) .. 31 Ordering Guide .. 64 DDC I/Q Input Selection .. 31
REVISION HISTORY 5/15—Revision 0: Initial Version
Rev. 0 | Page 2 of 64 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjustment Clock Fine Delay Adjustment Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR DIGITAL DOWNCONVERTERS (DDCs) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION BLOCK DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS DIGITAL OUTPUTS Timing Data Clock Output ADC OVERRANGE MULTICHIP SYNCHRONIZATION SYNC± SETUP AND HOLD WINDOW MONITOR TEST MODES ADC TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE
