Datasheet AD7177-2 (Analog Devices) - 2
| Manufacturer | Analog Devices |
| Description | 32-Bit, 10 kSPS, Sigma-Delta ADC with 100 µs Settling and True Rail-to-Rail Buffers |
| Pages / Page | 61 / 2 — AD7177-2* PRODUCT PAGE QUICK LINKS Last Content Update: 06/27/2017. … |
| Revision | B |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
AD7177-2* PRODUCT PAGE QUICK LINKS Last Content Update: 06/27/2017. COMPARABLE PARTS. REFERENCE MATERIALS. Technical Articles
Model Line for this Datasheet
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AD7177-2* PRODUCT PAGE QUICK LINKS Last Content Update: 06/27/2017 COMPARABLE PARTS REFERENCE MATERIALS
View a parametric search of comparable parts.
Technical Articles
• Fundamental Principles Behind the Sigma-Delta ADC
EVALUATION KITS
Topology: Part 1 • AD7177-2 Evaluation Board • Fundamental Principles Behind the Sigma-Delta ADC Topology: Part 2
DOCUMENTATION Tutorials Data Sheet
• MT-022: ADC Architectures III: Sigma-Delta ADC Basics • AD7177-2: 32-Bit, 10 kSPS, Sigma-Delta ADC with 100 μs • MT-023: ADC Architectures IV: Sigma-Delta ADC Settling and True Rail-to-Rail Buffers Data Sheet Advanced Concepts and Applications
Technical Books DESIGN RESOURCES
• The Data Conversion Handbook, 2005 • AD7177-2 Material Declaration
User Guides
• PCN-PDN Information • UG-849: Evaluating the AD7177-2 32-Bit, 10 kSPS, Sigma- Delta ADC with 100 µs Settling and Integrated Analog • Quality And Reliability Input Buffers • Symbols and Footprints
SOFTWARE AND SYSTEMS REQUIREMENTS DISCUSSIONS
• AD717x Microcontroller No-OS View all AD7177-2 EngineerZone Discussions. • AD717x Eval+ Software
SAMPLE AND BUY TOOLS AND SIMULATIONS
Visit the product page to see pricing options. • AD7177-2 Digital Filter Frequency Response Model • AD7177-2 IBIS Model
TECHNICAL SUPPORT
Submit a technical question or find your regional support
REFERENCE DESIGNS
number. • CN0292 • CN0364
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7177-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7177-2 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 24-BIT/32-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE
View a parametric search of comparable parts.
Technical Articles
• Fundamental Principles Behind the Sigma-Delta ADC
EVALUATION KITS
Topology: Part 1 • AD7177-2 Evaluation Board • Fundamental Principles Behind the Sigma-Delta ADC Topology: Part 2
DOCUMENTATION Tutorials Data Sheet
• MT-022: ADC Architectures III: Sigma-Delta ADC Basics • AD7177-2: 32-Bit, 10 kSPS, Sigma-Delta ADC with 100 μs • MT-023: ADC Architectures IV: Sigma-Delta ADC Settling and True Rail-to-Rail Buffers Data Sheet Advanced Concepts and Applications
Technical Books DESIGN RESOURCES
• The Data Conversion Handbook, 2005 • AD7177-2 Material Declaration
User Guides
• PCN-PDN Information • UG-849: Evaluating the AD7177-2 32-Bit, 10 kSPS, Sigma- Delta ADC with 100 µs Settling and Integrated Analog • Quality And Reliability Input Buffers • Symbols and Footprints
SOFTWARE AND SYSTEMS REQUIREMENTS DISCUSSIONS
• AD717x Microcontroller No-OS View all AD7177-2 EngineerZone Discussions. • AD717x Eval+ Software
SAMPLE AND BUY TOOLS AND SIMULATIONS
Visit the product page to see pricing options. • AD7177-2 Digital Filter Frequency Response Model • AD7177-2 IBIS Model
TECHNICAL SUPPORT
Submit a technical question or find your regional support
REFERENCE DESIGNS
number. • CN0292 • CN0364
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7177-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7177-2 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 24-BIT/32-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE
