Datasheet AD9681 (Analog Devices)

Octal, 14-Bit, 125 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter Data Sheet AD9681 FEATURES SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD Low power 8 ADC channels integrated into 1 package AD9681 SERIAL D0+A1 110 mW per channel at 125 MSPS with scalable power LVDS D0–A1 SERIAL D1+A1 options 14 VIN+A1 LVDS D1–A1 PIPELINE DIGITAL D0+A2 SNR: 74 dBFS (to Nyquist); SFDR: 90 dBc (to Nyquist) VIN–A1 ADC SERIALIZER SERIAL 14 LVDS D0–A2 DNL: ±0.8 LSB (typical); INL: ±1.2 LSB (typical) VIN+A2 PIPELINE DIGITAL SERIAL D1+A2 VIN–A2 ADC SERIALIZER LVDS Crosstalk, worst adjacent channel, 70 MHz, −1 dBFS: −83 dB D1–A2 typical Serial LVDS (ANSI-644, default) 14 SERIAL D0+D1 Low power, reduced signal option (similar to IEEE 1596.3) VIN+D1 PIPELINE DIGITAL LVDS D0–D1 VIN–D1 ADC SERIALIZER Data and frame clock outputs SERIAL D1+D1 14 VIN+D2 LVDS DIGITAL D1–D1 650 MHz full power analog bandwidth PIPELINE VIN–D2 ADC SERIALIZER SERIAL D0+D2 LVDS 2 V p-p input voltage range D0–D2 VREF D1+D2 SERIAL 1.8 V supply operation SENSE LVDS D1–D2 REF 1V VCM1, VCM2 Serial port control FCO+1, FCO+2 SELECT GND FCO–1, FCO–2 Flexible bit orientation DCO+1, DCO+2 SERIAL PORT CLOCK Built-in and custom digital test pattern generation INTERFACE MANAGEMENT DCO–1, DCO–2 Programmable clock and data alignment 2 C + – S LM TP N K K Power-down and standby modes IA /D B /O SY CL CL , CSB2 IO LK D C APPLICATIONS 1, R S S
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Communications receivers Multichannel data acquisition
The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data
GENERAL DESCRIPTION
alignment and programmable digital test pattern generation. The The AD9681 is an octal, 14-bit, 125 MSPS analog-to-digital available digital test patterns include built-in deterministic and converter (ADC) with an on-chip sample-and-hold circuit that pseudorandom patterns, along with custom user-defined test is designed for low cost, low power, small size, and ease of use. patterns entered via the serial port interface (SPI). The device operates at a conversion rate of up to 125 MSPS and The AD9681 is available in an RoHS-compliant, 144-ball is optimized for outstanding dynamic performance and low CSP-BGA. It is specified over the industrial temperature range of power in applications where a small package size is critical. −40°C to +85°C. This product is protected by a U.S. patent. The ADC requires a single 1.8 V power supply and an LVPECL-/
PRODUCT HIGHLIGHTS
CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are 1. Small Footprint. Eight ADCs are contained in a small, required for many applications. 10 mm × 10 mm package. 2. Low Power. The device dissipates 110 mW per channel at The AD9681 automatically multiplies the sample rate clock for 125 MSPS with scalable power options. the appropriate LVDS serial data rate. Data clock outputs (DCO±1, 3. Ease of Use. Data clock outputs (DCO±1, DCO±2) operate DCO±2) for capturing data on the output and frame clock outputs at frequencies of up to 500 MHz and support double data (FCO±1, FCO±2) for signaling a new output byte are provided. rate (DDR) operation. Individual channel power-down is supported, and the device 4. User Flexibility. SPI control offers a wide range of flexible typically consumes less than 2 mW when all channels are disabled. features to meet specific system requirements.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/OLM Pin SCLK/DTP Pin CSB1 and CSB2 Pins RBIAS1 and RBIAS2 Pins OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Enhancement Control (Register 0x0C) Output Mode (Register 0x14) Output Adjust (Register 0x15) Output Phase (Register 0x16) Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) User I/O Control 3 (Register 0x102) APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS BOARD LAYOUT CONSIDERATIONS Sources of Coupling Crosstalk Between Inputs Coupling of Digital Output Switching Noise to Analog Inputs and Clock CLOCK STABILITY CONSIDERATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE