Datasheet AD7961 (Analog Devices) - 6

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Data Sheet AD7961 Parameter Test Conditions/Comments Min Typ Max Unit
Power-Down EN3 to EN0 = X000 VDD1 1 2.8 μA VDD2 1 37.8 μA VIO 0.2 4.6 μA Power Dissipation Static—Not Converting, Internal Self clocked mode, CNV± in CMOS 9 10.3 mW Reference Buffer Disabled mode9 Static—Not Converting, Internal Self clocked mode, CNV± in CMOS 21 25 mW Reference Buffer Enabled mode9 Converting: Internal Reference Buffer Echoed clock mode, CNV± in LVDS 46.5 56.2 mW Disabled mode Converting: Internal Reference Buffer Echoed clock mode, CNV± in LVDS 64.5 76.4 mW Enabled mode Converting: Internal Reference Buffer Self clocked mode, CNV± in CMOS 39 47.4 mW Disabled mode9 Power-Down EN3 to EN0 = X000 7.2 94.5 μW Energy per Conversion Self clocked, CNV± in CMOS mode9 7.8 9.5 nJ/sample TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 The minimum and maximum values are guaranteed by characterization. 2 Using an external reference. 3 See Table 9 for logic levels of enable pins. When EN2 = 1, the −3 dB input bandwidth is 9 MHz. Use this lower bandwidth only when the throughput rate is 2 MSPS or lower. 4 The oversampled dynamic range is the ratio of the peak signal power to the noise power (for a small input) measured in the ADC output FFT from dc up to fS/(2 × OSR), where fS is the ADC sample rate and OSR is the oversampling ratio. 5 Guaranteed by design. 6 The REFIN pin is tied to 0 V in this mode. 7 The ANSI-644 LVDS specification has a minimum common-mode output (VOCM) of 1125 mV. 8 The current dissipated in the VCM circuitry when enabled is REF/20 kΩ and is not included in the operating currents listed. 9 CNV+ works as a CMOS input when CNV− is grounded. See Table 7 for additional information.
TIMING SPECIFICATIONS
VDD1 = 5 V; VDD2 = 1.8 V; VIO = 1.71 V to 1.89 V; REF = 5 V or 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Symbol Min Typ Max Unit
Time Between Conversions tCYC 200 ns Acquisition Time tACQ tCYC − 115 ns CNV± High Time tCNVH 10 0.6 × tCYC ns CNV± to D± (MSB) Ready tMSB 200 ns CNV± to Last CLK± (LSB) Delay tCLKL 160 ns CLK± Period1 tCLK 3.33 4 (tCYC − tMSB + tCLKL)/n ns CLK± Frequency fCLK 250 300 MHz CLK± to DCO± Delay (Echoed Clock Mode) tDCO 0 3 5 ns DCO± to D± Delay (Echoed Clock Mode) tD 0 1 ns CLK± to D± Delay tCLKD 0 3 5 ns 1 For the maximum CLK± period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) to be read giving the maximum CLK± frequency that can be used for a given conversion CNV± frequency. In echoed clock interface mode, n = 16; in self clocked interface mode, n = 18. Rev. B | Page 5 of 24 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Information Transfer Function Analog Inputs Typical Applications Voltage Reference Options Wake-Up Time from Power-Down and Snooze Modes Power Supply Power-Up Digital Interface Conversion Control Echoed Clock Interface Mode Self Clocked Mode Applications Information Layout Evaluating AD7961 Performance Outline Dimensions Ordering Guide