Datasheet ADAS3023 (Analog Devices) - 5

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ADAS3023 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit1
Dynamic Range fIN = 1 kHz, −60 dB input PGIA gain = 0.2 91.0 92 dB PGIA gain = 0.4 90.5 91.5 dB PGIA gain = 0.8 88.0 89.5 dB PGIA gain = 1.6 86.0 87.0 dB Total Harmonic Distortion fIN = 1 kHz, all PGIA gains −100 dB Spurious-Free Dynamic Range fIN = 1 kHz, all PGIA gains 105 dB Channel-to-Channel Crosstalk fIN = 1 kHz, all channels inactive 95 dB DC Common-Mode Rejection Ratio All channels (CMRR) PGIA gain = 0.2 95.0 dB PGIA gain = 0.4 95.0 dB PGIA gain = 0.8 95.0 dB PGIA gain = 1.6 95.0 dB −3 dB Input Bandwidth −40 dBFS 8 MHz INTERNAL REFERENCE REFx Pins Output Voltage TA = 25°C 4.088 4.096 4.104 V Output Current TA = 25°C 250 µA Temperature Drift REFEN bit = 1 ±5 ppm/°C REFEN bit = 0, REFIN pin = 2.5V ±1 ppm/°C Line Regulation Internal Reference AVDD = 5 V ± 5% 20 μV/V Buffer Only AVDD = 5 V ± 5% 4 ppm REFIN Output Voltage6 TA = 25°C 2.495 2.5 2.505 V Turn-On Settling Time CREFIN, CREF1, CREF2 = 10 µF||0.1 µF 100 ms EXTERNAL REFERENCE REFEN bit = 0 Voltage Range REFx input, REFIN = 0 V 4.000 4.096 4.104 V REFIN input (buffered) 2.5 2.505 V Current Drain fS = 500 kSPS 100 µA DIGITAL INPUTS Logic Levels VIL VIO > 3 V −0.3 +0.3 × VIO V VIH VIO > 3 V 0.7 × VIO VIO + 0.3 V VIL VIO ≤ 3 V −0.3 +0.1 × VIO V VIH VIO ≤ 3 V 0.9 × VIO VIO + 0.3 V IIL −1 +1 µA IIH −1 +1 µA DIGITAL OUTPUTS7 Data Format Twos complement VOL ISINK = +500 µA 0.4 V VOH ISOURCE = −500 µA VIO − 0.3 V POWER SUPPLIES VIO 1.8 AVDD + 0.3 V AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V VDDH VDDH > input voltage + 2.5 V 14.25 15 15.75 V VSSH VSSH < input voltage − 2.5 V −15.75 −15 −14.25 V Rev. A | Page 4 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Circuit and Voltage Diagrams Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview Operation Transfer Functions Typical Application Connection Diagram Analog Inputs Input Structure Programmable Gain Common-Mode Operating Range Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) Single-Ended Signals with a 0 V DC Offset (Symmetrical) Voltage Reference Input/Output Internal Reference External Reference and Internal Buffer External Reference Reference Decoupling Power Supply Core Supplies High Voltage Supplies Power Dissipation Modes Fully Operational Mode Power-Down Mode Conversion Modes Warp Mode (CMS = 0) Normal Mode (CMS = 1, Default) Digital Interface Conversion Control CNV Rising--Start of Conversion (SOC) BUSY/SDO2 Falling Edge—End of Conversion (EOC) Register Pipeline RESET and Power-Down (PD) Inputs Serial Data Interface General Timing Configuration Register Packaging and Ordering Information Outline Dimensions Ordering Guide