Datasheet ADAS3023 (Analog Devices) - 7

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ADAS3023 Data Sheet TIMING SPECIFICATIONS
VDDH = 15 V ± 5%, VSSH = −15 V ± 5%, AVDD = DVDD = 5 V ± 5%, VIO = 1.8 V to AVDD, Internal Reference VREF = 4.096 V, fS = 500 kSPS, all specifications TMIN to TMAX, unless otherwise noted.1
Table 3. Parameter Symbol Min Typ Max Unit
TIME BETWEEN CONVERSIONS tCYC Warp2 Mode, CMS = 0 Two Channels 2.0 1000 µs Four Channels 4.0 1000 µs Six Channels 6.0 1000 µs Eight Channels 8.0 1000 µs Normal Mode (Default), CMS = 1 Two Channels 2.1 1000 µs Four Channels 4.1 1000 µs Six Channels 6.1 1000 µs Eight Channels 8.1 1000 µs CONVERSION TIME: CNV RISING EDGE TO DATA AVAILABLE tCONV Warp Mode, CMS = 0 Two Channels 1485 1630 ns Four Channels 2850 3340 ns Six Channels 4215 5000 ns Eight Channels 5580 6700 ns Normal Mode (Default), CMS = 1 Two Channels 1575 1720 ns Four Channels 2940 3430 ns Six Channels 4305 5090 ns Eight Channels 5670 6790 ns CNV Pulse Width tCNVH 10 ns CNV High to Hold Time (Aperture Delay) tAD 2 ns CNV High to BUSY/SDO2 Delay tCBD 520 ns SCK Period tSCK tSDOV + 3 ns Low Time tSCKL 5 ns High Time tSCKH 5 ns SCK Falling Edge to Data Remains Valid tSDOH 4 ns SCK Falling Edge to Data Valid Delay tSDOV VIO > 4.5 V 12 ns VIO > 3 V 18 ns VIO > 2.7 V 24 ns VIO > 2.3 V 25 ns VIO > 1.8 V 37 ns CS/RESET/PD CS/RESET/PD Low to SDO D15 MSB Valid tEN VIO > 4.5 V 7 ns VIO > 3 V 8 ns VIO > 2.7 V 10 ns VIO > 2.3 V 15 ns VIO > 1.8 V 20 ns CS/RESET/PD High to SDO High Impedance tDIS 25 ns CNV Rising to CS tCCS 5 ns Rev. A | Page 6 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Circuit and Voltage Diagrams Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview Operation Transfer Functions Typical Application Connection Diagram Analog Inputs Input Structure Programmable Gain Common-Mode Operating Range Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) Single-Ended Signals with a 0 V DC Offset (Symmetrical) Voltage Reference Input/Output Internal Reference External Reference and Internal Buffer External Reference Reference Decoupling Power Supply Core Supplies High Voltage Supplies Power Dissipation Modes Fully Operational Mode Power-Down Mode Conversion Modes Warp Mode (CMS = 0) Normal Mode (CMS = 1, Default) Digital Interface Conversion Control CNV Rising--Start of Conversion (SOC) BUSY/SDO2 Falling Edge—End of Conversion (EOC) Register Pipeline RESET and Power-Down (PD) Inputs Serial Data Interface General Timing Configuration Register Packaging and Ordering Information Outline Dimensions Ordering Guide