Datasheet AD9683 (Analog Devices) - 9

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AD9683 Data Sheet SWITCHING SPECIFICATIONS Table 4. AD9683-170 AD9683-250 Parameter Symbol Temperature Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS Conversion Rate1 fS Full 40 170 40 250 MSPS SYSREF± Setup Time to Rising Edge CLK±2 tREFS Full 300 300 ps SYSREF± Hold Time from Rising Edge CLK±2 tREFH Full 40 40 ps SYSREF± Setup Time to Rising Edge RFCLK±2 tREFSRF Full 400 400 ps SYSREF± Hold Time from Rising Edge RFCLK±2 tREFHRF Full 0 0 ps CLK± Pulse Width High tCH Divide-by-1 Mode, DCS Enabled Full 2.61 2.9 3.19 1.8 2.0 2.2 ns Divide-by-1 Mode, DCS Disabled Full 2.76 2.9 3.05 1.9 2.0 2.1 ns Divide-by-2 Mode Through Divide-by-8 Mode Full 0.8 0.8 ns Aperture Delay tA Full 1.0 1.0 ns Aperture Uncertainty (Jitter) tJ Full 0.16 0.16 ps rms DATA OUTPUT PARAMETERS Data Output Period or Unit Interval (UI) Full 20 × fS 20 × fS Seconds Data Output Duty Cycle 25°C 50 50 % Data Valid Time 25°C 0.82 0.78 UI PLL Lock Time tLOCK 25°C 25 25 µs Wake-Up Time Standby 25°C 10 10 µs ADC (Power-Down)3 25°C 250 250 µs Output (Power-Down)4 25°C 50 50 µs Subclass 0: SYNCINB± Falling Edge to First Valid Full 5 5 Multiframes K.28 Characters (Delay Required for Rx CGS Start) Subclass 1: SYSREF± Rising Edge to First Valid K.28 Full 6 6 Multiframes Characters (Delay Required for SYNCINB± Rising Edge/Rx CGS Start) CGS Phase K.28 Characters Duration Full 1 1 Multiframe Pipeline Delay JESD204B (Latency) Full 36 36 Cycles5 Fast Detect (Latency) Full 7 7 Cycles5 Lane Rate Full 3.4 5 5 Gbps Uncorrelated Bounded High Probability (UBHP) Jitter Full 10 12 ps Random Jitter At 3.4 Gbps Full 2.4 ps rms At 5 Gbps Full 1.7 ps rms Output Rise/Fall Time Full 60 60 ps Differential Termination Resistance 25°C 100 100 Ω Out-of-Range Recovery Time Full 3 3 Cycles5 1 Conversion rate is the clock rate after the divider. 2 Refer to Figure 3 for timing diagram. 3 Wake-up time ADC is defined as the time required for the ADC to return to normal operation from power-down mode. 4 Wake-up time output is defined as the time required for JESD204B output to return to normal operation from power-down mode. 5 Cycles refers to ADC conversion rate cycles. Rev. D | Page 8 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS JESD204B TRANSMIT TOP LEVEL DESCRIPTION JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lane Before Changing Configuration Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lane After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC OVERRANGE AND GAIN CONTROL ADC Overrange (OR) Gain Switching Fast Threshold Detection (FD) DC CORRECTION (DCC) DC CORRECTION BANDWIDTH DC CORRECTION READBACK DC CORRECTION FREEZE DC CORRECTION ENABLE BITS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS PDWN Modes (Address 0x08) Output Mode (Address 0x14) SYNCINB±/SYSREF± Control (Address 0x3A) DC Correction Control (Address 0x40) DC Correction Value 0 (Address 0x41) DC Correction Value 1 (Address 0x42) Fast Detect Control (Address 0x45) Fast Detect Upper Threshold (Address 0x47 and Address 0x48) Fast Detect Lower Threshold (Address 0x49 and Address 0x4A) Fast Detect Dwell Time (Address 0x4B and Address  0x4C) JESD204B Quick Configuration (Address 0x5E) JESD204B Link Control 1 (Address 0x5F) JESD204B Link Control 2 (Address 0x60) JESD204B Link Control 3 (Address 0x61) JESD204B Device Identification (DID) Configuration (Address 0x64) JESD204B Bank Identification (BID) Configuration (Address 0x65) JESD204B Lane Identification (LID) Configuration (Address 0x67) JESD204B Scrambler (SCR) and Lane (L) Configuration (Address 0x6E) JESD204B Parameter, F (Address 0x6F, Read Only) JESD204B Parameter, K (Address 0x70) JESD204B Parameter, M (Address 0x71) JESD204B Parameters, N/CS (Address 0x72) JESD204B Parameter, Subclass/N’ (Address 0x73) JESD204B Samples per Converter per Frame Cycle (S) (Address 0x74) JESD204B Parameters HD and CF (Address 0x75) JESD204B Reserved 1 (Address 0x76) JESD204B Reserved 2 (Address 0x77) JESD204B Checksum (Address 0x79) JESD204B Output Driver Control (Address 0x80) JESD204B LMFC Offset (Address 0x8B) JESD204B Preemphasis (Address 0xA8) APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Pad Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE