Datasheet AD7176-2 (Analog Devices) - 7

AD7176-2 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
POWER REQUIREMENTS Power Supply Voltage AVDD1 − AVSS 4.5 5.5 V AVDD2 – AVSS 2 5.5 V AVSS – DGND −2.75 0 V IOVDD − DGND 2 5.5 V IOVDD – AVSS For AVSS < DGND 6.35 V POWER SUPPLY CURRENTS All outputs unloaded, digital inputs connected to IOVDD or DGND Full Operating Mode AVDD1 Current External reference 1.5 1.8 mA Internal reference 1.8 2.1 mA AVDD2 Current External reference 4.3 4.9 mA Internal reference 4.5 5.1 mA IOVDD Current External clock 2 2.3 mA Internal clock 2.3 2.6 mA External crystal 2.5 mA Standby Mode Standby (LDO On) Internal reference off, total current 22 µA consumption Internal reference on, total current 415 µA consumption Power-Down Mode Full power-down, LDO, Internal 0.5 10 µA reference POWER DISSIPATION Full Operating Mode AVDD2 = 2 V, IOVDD = 2 V, 20.1 23.2 mW external clock and reference AVDD2 = 5 V, IOVDD = 5 V, 39 44.8 mW external clock and reference AVDD2 = 2 V, IOVDD = 2 V, 22.3 25.9 mW internal clock and reference AVDD2 = 5 V, IOVDD = 5 V, 42.5 49 mW internal clock and reference Standby Mode Internal reference off, all supplies = 5 V 110 µW Internal reference on, all supplies = 5 V 2.1 mW Power-Down Mode Full power-down 2.5 50 µW 1 Specification is not production tested but is supported by characterization data at the initial product release. 2 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration reduces the gain error to the order of the noise for the programmed output data rate. 3 This specification is noncumulative and includes the effects of preconditioning. 4 This specification includes MSL preconditioning effects. Rev. D | Page 6 of 68 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7176-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Fully Differential Inputs Pseudo Differential Inputs DRIVER AMPLIFIERS AD8475 AD8656 ADA4940-1/ADA4940-2 AD7176-2 REFERENCE External Reference Internal Reference AD7176-2 CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION (SYNC\/ERROR\) ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Pin DATA_STAT IOSTRENTGH GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL MAP REGISTER 0 CHANNEL MAP REGISTER 1 CHANNEL MAP REGISTER 2 CHANNEL MAP REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 SETUP CONFIGURATION REGISTER 2 SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 FILTER CONFIGURATION REGISTER 2 FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 OFFSET REGISTER 2 OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 GAIN REGISTER 2 GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE