Datasheet AD9635 (Analog Devices) - 2

AD9635* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS REFERENCE MATERIALS
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Press
• Analog Devices’ Dual 14-bit A/D Converter Reduces
EVALUATION KITS
Power and Size in Communications, Instrumentation, Test and Measurement Applications • AD9635 Evalution Board
Technical Articles DOCUMENTATION
• MS-2210: Designing Power Supplies for High Speed ADC
Application Notes DESIGN RESOURCES
• AN-1142: Techniques for High Speed ADC PCB Layout • AD9635 Material Declaration • AN-501: Aperture Uncertainty and ADC System Performance • PCN-PDN Information • AN-737: How ADIsimADC Models an ADC • Quality And Reliability • AN-827: A Resonant Approach to Interfacing Amplifiers to • Symbols and Footprints Switched-Capacitor ADCs • AN-835: Understanding High Speed ADC Testing and
DISCUSSIONS
Evaluation View all AD9635 EngineerZone Discussions. • AN-878: High Speed ADC SPI Control Software • AN-905: Visual Analog Converter Evaluation Tool Version
SAMPLE AND BUY
1.0 User Manual Visit the product page to see pricing options. • AN-935: Designing an ADC Transformer-Coupled Front End
TECHNICAL SUPPORT Data Sheet
Submit a technical question or find your regional support • AD9635: Dual, 12-Bit, 80 MSPS/125 MSPS, Serial LVDS 1.8 number. V Analog-to-Digital Converter
User Guides DOCUMENT FEEDBACK
• AD9655/AD9645/AD9635 Evaluation Documentation Submit feedback for this data sheet.
TOOLS AND SIMULATIONS
• Visual Analog • AD9635 IBIS Model • AD9635 S-Parameter
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9635-80 AD9635-125 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE