Datasheet AD9637 (Analog Devices) - 10

Data Sheet AD9637 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS F F E E D D C C + – D – + D F + – D – + N N D N N D M E IAS N N D N N VI VI AV VI VI AV SYNC VC VR SENSE RB VI VI AV VI VI 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PIN 1 INDICATOR AVDD 1 48 AVDD VIN+ G 2 47 VIN+ B VIN– G 3 46 VIN– B AVDD 4 45 AVDD VIN– H 5 44 VIN– A VIN+ H 6 43 VIN+ A AVDD 7 AD9637 42 AVDD AVDD 8 41 PDWN TOP VIEW CLK– 9 40 CSB (Not to Scale) CLK+ 10 39 SDIO/DFS AVDD 11 38 SCLK/DTP AVDD 12 37 AVDD DNC 13 36 DNC DRVDD 14 35 DRVDD D– H 15 34 D+ A D+ H 16 33 D– A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 – + – G F E O O O+ D C B D– G D+ D– F D+ D– E D+ D– D D+ D– C D+ D– B D+ DC DCO FC FC NOTES
5
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
-00
2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.
0215 1 Figure 5. Pin Configuration, Top View
Table 8. Pin Function Descriptions Pin No. Mnemonic Description
0, EP AGND, Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the Exposed Pad analog ground for the part. This exposed pad must be connected to analog ground for proper operation. 1, 4, 7, 8, 11, AVDD 1.8 V Analog Supply. 12, 37, 42, 45, 48, 51, 59, 62 13, 36 DNC Do Not Connect. Do not connect to this pin. 14, 35 DRVDD 1.8 V Digital Output Driver Supply. 2, 3 VIN+ G, VIN− G ADC G Analog Input True, ADC G Analog Input Complement. 5, 6 VIN− H, VIN+ H ADC H Analog Input Complement, ADC H Analog Input True. 9, 10 CLK−, CLK+ Input Clock Complement, Input Clock True. 15, 16 D− H, D+ H ADC H Digital Output Complement, ADC H Digital Output True. 17, 18 D− G, D+ G ADC G Digital Output Complement, ADC G Digital Output True. 19, 20 D− F, D+ F ADC F Digital Output Complement, ADC F Digital Output True. 21, 22 D− E, D+ E ADC E Digital Output Complement, ADC E Digital Output True. 23, 24 DCO−, DCO+ Data Clock Digital Output Complement, Data Clock Digital Output True. 25, 26 FCO−, FCO+ Frame Clock Digital Output Complement, Frame Clock Digital Output True. 27, 28 D− D, D+ D ADC D Digital Output Complement, ADC D Digital Output True. 29, 30 D− C, D+ C ADC C Digital Output Complement, ADC C Digital Output True. 31, 32 D− B, D+ B ADC B Digital Output Complement, ADC B Digital Output True. 33, 34 D− A, D+ A ADC A Digital Output Complement, ADC A Digital Output True. 38 SCLK/DTP Serial Clock (SCLK)/Digital Test Pattern (DTP). 39 SDIO/DFS Serial Data Input/Output (SDIO)/Data Format Select (DFS). 40 CSB Chip Select Bar. 41 PDWN Power-Down. 43, 44 VIN+ A, VIN− A ADC A Analog Input True, ADC A Analog Input Complement. 46, 47 VIN− B, VIN+ B ADC B Analog Input Complement, ADC B Analog Input True. 49, 50 VIN+ C, VIN− C ADC C Analog Input True, ADC C Analog Input Complement. Rev. A | Page 9 of 40 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9637-80 AD9637-40 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/DFS Pin SCLK/DTP Pin CSB Pin RBIAS Pin Built-In Output Test Modes Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x04 and Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Outline Dimensions Ordering Guide