Datasheet AD9634 (Analog Devices)

12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter Data Sheet AD9634 FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 69.7 dBFS at 185 MHz AIN and 250 MSPS AVDD AGND DRVDD SFDR = 87 dBc at 185 MHz AIN and 250 MSPS −150.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and VIN+ PIPELINE 12 D0±/D1± 12-BIT . 250 MSPS VIN– ADC . PARALLEL . Total power consumption: 360 mW at 250 MSPS DDR LVDS VCM AD9634 AND D10±/D11± 1.8 V supply voltages DRIVERS LVDS (ANSI-644 levels) outputs REFERENCE DCO± Integer 1-to-8 input clock divider (625 MHz maximum input) Sample rates of up to 250 MSPS OR± Internal ADC voltage reference 1-TO-8 SERIAL PORT CLOCK DIVIDER Flexible analog input range
001
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) SCLK SDIO CSB CLK+ CLK–
09996-
ADC clock duty cycle stabilizer
Figure 1.
Serial port control Energy-saving power-down modes APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications GENERAL DESCRIPTION
The AD9634 is a 12-bit, analog-to-digital converter (ADC) with Programming for setup and control is accomplished using a sampling speeds of up to 250 MSPS. The AD9634 is designed to 3-wire, SPI-compatible serial interface. support communications applications where low cost, small size, The AD9634 is available in a 32-lead LFCSP and is specified over wide bandwidth, and versatility are desired. the industrial temperature range of −40°C to +85°C. This product The ADC core features a multistage, differential pipelined is protected by a U.S. patent. architecture with integrated output error correction logic. The
PRODUCT HIGHLIGHTS
ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference 1. Integrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC. eases design considerations. A duty cycle stabilizer (DCS) is 2. Fast overrange and threshold detect. provided to compensate for variations in the ADC clock duty cycle, 3. Proprietary differential input maintains excellent SNR al owing the converter to maintain excellent performance. performance for input frequencies of up to 350 MHz. 4. 3-pin, 1.8 V SPI port for register programming and readback. The ADC output data are routed directly to the external 12-bit 5. Pin compatibility with the AD9642, allowing a simple LVDS output port. migration up to 14 bits, and with the AD6672. Flexible power-down options allow significant power savings, when desired.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC OVERRANGE (OR) SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE