link to page 4 link to page 4 link to page 4 link to page 4 link to page 26 link to page 26 link to page 5 link to page 4 link to page 4 link to page 4 link to page 4 Data SheetAD9434SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted. Table 1 .AD9434-370AD9434-500Parameter1TempMinTypMaxMinTypMaxUnit RESOLUTION 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error 25°C ±0.25 ±0.25 mV Full −3.0 +1.0 −3.0 +1.0 mV Gain Error 25°C 1.0 1.0 % FS Full −5.0 +7.0 −5.0 +7.0 % FS Differential Nonlinearity (DNL) 25°C ±0.4 ±0.5 LSB Full −0.9 +0.9 −0.95 +1.0 LSB Integral Nonlinearity (INL) 25°C ±0.4 ±0.6 LSB Full −0.92 +0.92 −1.3 +1.3 LSB INTERNAL REFERENCE VREF Full 0.71 0.75 0.78 0.71 0.75 0.78 V TEMPERATURE DRIFT Offset Error Full 18 18 µV/°C Gain Error Full 0.07 0.07 %/°C ANALOG INPUTS (VIN+, VIN−) Differential Input Voltage Range2 Full 1.18 1.5 1.6 1.18 1.5 1.6 V p-p Input Common-Mode Voltage Full 1.7 1.7 V Input Resistance (Differential) Full 1 1 kΩ Input Capacitance (Differential) 25°C 1.3 1.3 pF POWER SUPPLY AVDD Full 1.75 1.8 1.9 1.75 1.8 1.9 V DRVDD Full 1.75 1.8 1.9 1.75 1.8 1.9 V Supply Currents I 3 AVDD Full 260 280 283 301 mA I 3 DRVDD /SDR Mode4 Full 88 100 100 114 mA I 3 DRVDD /DDR Mode5 Full 70 80 82 96 mA Power Dissipation SDR Mode4 Full 625 685 690 747 mW DDR Mode5 Full 595 648 657 715 mW Standby Mode Full 40 50 40 50 mW Power-Down Mode Full 2.5 7 2.5 7 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. 3 IAVDD and IDRVDD are measured with a −1 dBFS, 30.3 MHz sine input at rated sample rate. 4 Single data rate mode; this is the default mode of the AD9434. 5 Double data rate mode; user-programmable feature. See the Memory Map section. Rev. B | Page 3 of 28 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input and Voltage Reference Differential Input Configurations Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) Timing VREF AD9434 Configuration Using the SPI Using the AD9434 to Replace the AD9230 Hardware Interface Configuration Without the SPI Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Outline Dimensions Ordering Guide