Datasheet AD9266 (Analog Devices)

ManufacturerAnalog Devices
Description16-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter
Pages / Page33 / 1 — 16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,. 1.8 V Analog-to-Digital …
RevisionB
File Format / SizePDF / 1.1 Mb
Document LanguageEnglish

16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,. 1.8 V Analog-to-Digital Converter. Data Sheet. AD9266. FEATURES

Datasheet AD9266 Analog Devices, Revision: B

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16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter Data Sheet AD9266 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation AVDD AGND SDIO SCLK CSB DRVDD 1.8 V to 3.3 V output supply RBIAS SNR SPI AD9266 VCM 77.6 dBFS at 9.7 MHz input OR R 71.1 dBFS at 200 MHz input FFE VIN+ PROGRAMMING DATA D15_D14 S U ADC O SFDR 8 CORE T B VIN– CM U D1_D0 93 dBc at 9.7 MHz input TP OU 80 dBc at 200 MHz input DCO VREF Low power SENSE 56 mW at 20 MSPS REF 113 mW at 80 MSPS SELECT Differential input with 700 MHz bandwidth DIVIDE DUTY CYCLE MODE On-chip voltage reference and sample-and-hold circuit 1 TO 8 STABILIZER CONTROLS
001
2 V p-p differential analog input CLK+ CLK– PDWN DFS MODE
08678-
DNL = −0.6/+1.1 LSB
Figure 1.
Interleaved data output for reduced pin-count interface Serial port control options Offset binary, Gray code, or twos complement data format Optional clock duty cycle stabilizer PRODUCT HIGHLIGHTS Integer 1-to-8 input clock divider Built-in selectable digital test pattern generation
1. The AD9266 operates from a single 1.8 V analog power
Energy-saving power-down modes
supply and features a separate digital output driver supply
Data clock output (DCO) with programmable clock and
to accommodate 1.8 V to 3.3 V logic families.
data alignment
2. The sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is
APPLICATIONS
designed for low cost, low power, and ease of use.
Communications
3. A standard serial port interface supports various product
Diversity radio systems
features and functions, such as data output formatting,
Multimode digital receivers
internal clock divider, power-down, DCO and data output
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
(D15_D14 to D1_D0) timing and offset adjustments, and
Smart antenna systems
voltage reference modes.
Battery-powered instruments
4. The AD9266 is packaged in a 32-lead RoHS-compliant
Handheld scope meters
LFCSP that is pin compatible with the AD9609 10-bit
Portable medical imaging
ADC, the AD9629 12-bit ADC, and the AD9649 14-bit
Ultrasound
ADC, enabling a simple migration path between 10-bit and
Radar/LIDAR
16-bit converters sampling from 20 MSPS to 80 MSPS.
PET/SPECT imaging Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2010–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9266-80 AD9266-65 AD9266-40 AD9266-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS USR2 (Register 0x101) Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE