Datasheet AD9262 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC |
| Pages / Page | 33 / 4 — AD9262. SPECIFICATIONS DC SPECIFICATIONS. Table 1. AD9262BCPZ … |
| Revision | A |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
AD9262. SPECIFICATIONS DC SPECIFICATIONS. Table 1. AD9262BCPZ AD9262BCPZ-5. AD9262BCPZ-10. Parameter Temp. Min Typ. Max Min Typ
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AD9262 SPECIFICATIONS DC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN1 = −2.0 dBFS, unless otherwise noted.
Table 1. AD9262BCPZ AD9262BCPZ-5 AD9262BCPZ-10 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 16 16 16 Bits ANALOG INPUT BANDWIDTH 2.5 5 10 MHz ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.025 ±0.2 ±0.025 ±0.2 ±0.025 ±0.2 % FSR Gain Error Full ±0.7 ±3.0 ±0.7 ±3.0 ±0.7 ±3.0 % FSR Integral Nonlinearity (INL)2 25°C ±1.5 ±1.5 ±1.5 LSB MATCHING CHARACERISTICS Offset Error Full ±0.035 ±0.2 ±0.035 ±0.2 ±0.035 ±0.2 % FSR Gain Error Full ±0.3 ±1.3 ±0.3 ±1.3 ±0.3 ±1.3 % FSR TEMPERATURE DRIFT Offset Error Full ±1.5 ±1.5 ±1.5 ppm/°C Gain Error Full ±50 ±50 ±50 ppm/°C INTERNAL VOLTAGE REFERENCE 490 500 510 490 500 510 490 500 510 mV ANALOG INPUT Input Span, VREF = 0.5 V Full 2 2 2 V p-p diff Common-Mode Voltage Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Input Resistance Full 1 1 1 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V CVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 3.6 1.7 1.8 3.6 1.7 1.8 3.6 V Supply Current I 2 AVDD Full 146 165 146 165 146 165 mA I 2 CVDD PLL Enabled Full 57 65 57 65 57 65 mA I 2 CVDD PLL Disabled Full 8.1 8.8 8.1 8.8 8.1 8.8 mA I 2 DVDD Full 108 117 141 152 169 182 mA I 2 DRVDD (1.8 V) Full 8.3 8.6 8.7 9.1 10 12.7 mA I 2 DRVDD (3.3 V) Full 17 18 22 mA POWER CONSUMPTION Sine Wave Input2 PLL Disabled Full 487 538.5 547 601.5 600 660 mW Sine Wave Input2 PLL Enabled Full 576 640 636 703 688 762 mW Power-Down Power Full 23 23 23 mW Standby Power2 Full 10 10 10 mW Sleep Power Full 3 4 3 4 3 4 mW 1 Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted. 2 Measured with a low input frequency, full-scale sine wave. Rev. A | Page 3 of 32 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Decimation Filtering Characteristics Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9262BCPZ AD9262BCPZ-5 AD9262BCPZ-10 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution PLL Autoband Select Jitter Considerations Power Dissipation and Standby Mode Digital Engine Bandwidth Selection Decimation Filters Sample Rate Converter Cascaded Filter Responses DC and Quadrature Error Correction (QEC) LO Leakage (DC) Correction QEC and DC Correction Range Digital Outputs Digital Output Format Interleaved Outputs Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Applications Information Filtering Requirement Memory Map Memory Map Definitions Outline Dimensions Ordering Guide
AD9262 SPECIFICATIONS DC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN1 = −2.0 dBFS, unless otherwise noted.
Table 1. AD9262BCPZ AD9262BCPZ-5 AD9262BCPZ-10 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 16 16 16 Bits ANALOG INPUT BANDWIDTH 2.5 5 10 MHz ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.025 ±0.2 ±0.025 ±0.2 ±0.025 ±0.2 % FSR Gain Error Full ±0.7 ±3.0 ±0.7 ±3.0 ±0.7 ±3.0 % FSR Integral Nonlinearity (INL)2 25°C ±1.5 ±1.5 ±1.5 LSB MATCHING CHARACERISTICS Offset Error Full ±0.035 ±0.2 ±0.035 ±0.2 ±0.035 ±0.2 % FSR Gain Error Full ±0.3 ±1.3 ±0.3 ±1.3 ±0.3 ±1.3 % FSR TEMPERATURE DRIFT Offset Error Full ±1.5 ±1.5 ±1.5 ppm/°C Gain Error Full ±50 ±50 ±50 ppm/°C INTERNAL VOLTAGE REFERENCE 490 500 510 490 500 510 490 500 510 mV ANALOG INPUT Input Span, VREF = 0.5 V Full 2 2 2 V p-p diff Common-Mode Voltage Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Input Resistance Full 1 1 1 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V CVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 3.6 1.7 1.8 3.6 1.7 1.8 3.6 V Supply Current I 2 AVDD Full 146 165 146 165 146 165 mA I 2 CVDD PLL Enabled Full 57 65 57 65 57 65 mA I 2 CVDD PLL Disabled Full 8.1 8.8 8.1 8.8 8.1 8.8 mA I 2 DVDD Full 108 117 141 152 169 182 mA I 2 DRVDD (1.8 V) Full 8.3 8.6 8.7 9.1 10 12.7 mA I 2 DRVDD (3.3 V) Full 17 18 22 mA POWER CONSUMPTION Sine Wave Input2 PLL Disabled Full 487 538.5 547 601.5 600 660 mW Sine Wave Input2 PLL Enabled Full 576 640 636 703 688 762 mW Power-Down Power Full 23 23 23 mW Standby Power2 Full 10 10 10 mW Sleep Power Full 3 4 3 4 3 4 mW 1 Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted. 2 Measured with a low input frequency, full-scale sine wave. Rev. A | Page 3 of 32 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Decimation Filtering Characteristics Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9262BCPZ AD9262BCPZ-5 AD9262BCPZ-10 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution PLL Autoband Select Jitter Considerations Power Dissipation and Standby Mode Digital Engine Bandwidth Selection Decimation Filters Sample Rate Converter Cascaded Filter Responses DC and Quadrature Error Correction (QEC) LO Leakage (DC) Correction QEC and DC Correction Range Digital Outputs Digital Output Format Interleaved Outputs Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Applications Information Filtering Requirement Memory Map Memory Map Definitions Outline Dimensions Ordering Guide
