Datasheet AD9265 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter |
| Pages / Page | 45 / 3 — AD9265. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 8/13—Rev. B to … |
| Revision | C |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
AD9265. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 8/13—Rev. B to Rev. C. 3/13—Rev. A to Rev. B. 1/10—Rev. 0 to Rev. A
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AD9265 Data Sheet TABLE OF CONTENTS
Features .. 1 Voltage Reference ... 28 Applications ... 1 Clock Input Considerations .. 29 Product Highlights ... 1 Power Dissipation and Standby Mode .. 31 Functional Block Diagram .. 1 Digital Outputs ... 32 Revision History ... 2 Timing.. 32 General Description ... 3 Built-In Self-Test (BIST) and Output Test .. 33 Specifications ... 4 Built-In Self-Test (BIST) .. 33 ADC DC Specifications ... 4 Output Test Modes ... 33 ADC AC Specifications ... 5 Serial Port Interface (SPI) .. 34 Digital Specifications ... 6 Configuration Using the SPI ... 34 Switching Specifications .. 8 Hardware Interface ... 34 Timing Specifications .. 9 Configuration Without the SPI .. 35 Absolute Maximum Ratings .. 10 SPI Accessible Features .. 35 Thermal Characteristics .. 10 Memory Map .. 36 ESD Caution .. 10 Reading the Memory Map Register Table ... 36 Pin Configurations and Function Descriptions ... 11 Memory Map Register Table ... 37 Typical Performance Characteristics ... 15 Memory Map Register Descriptions .. 39 Equivalent Circuits ... 23 Applications Information .. 40 Theory of Operation .. 25 Design Guidelines .. 40 ADC Architecture .. 25 Outline Dimensions ... 41 Analog Input Considerations .. 25 Ordering Guide .. 41
REVISION HISTORY 8/13—Rev. B to Rev. C
Changes to Data Clock Output (DCO) Section ... 32 Changes to Ordering Guide .. 41
3/13—Rev. A to Rev. B
Changes to Table 17 .. 37 Updated Outline Dimensions ... 41
1/10—Rev. 0 to Rev. A
Changes to Worst Other (Harmonic or Spur) Parameter, Table 2 .. 5 Changes to Figure 77 .. 29 Changes to Input Clock Divider Section ... 30 Changes to Table 17 .. 37 Updated Outline Dimensions ... 41
10/09—Revision 0: Initial Version
Rev. C | Page 2 of 44 Document Outline Features Applications Product Highlights Functional Block Diagram Table of Contents Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Dither Large Signal FFT Small Signal FFT Static Linearity Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Clock Duty Cycle Input Clock Divider Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Applications Information Design Guidelines Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide
AD9265 Data Sheet TABLE OF CONTENTS
Features .. 1 Voltage Reference ... 28 Applications ... 1 Clock Input Considerations .. 29 Product Highlights ... 1 Power Dissipation and Standby Mode .. 31 Functional Block Diagram .. 1 Digital Outputs ... 32 Revision History ... 2 Timing.. 32 General Description ... 3 Built-In Self-Test (BIST) and Output Test .. 33 Specifications ... 4 Built-In Self-Test (BIST) .. 33 ADC DC Specifications ... 4 Output Test Modes ... 33 ADC AC Specifications ... 5 Serial Port Interface (SPI) .. 34 Digital Specifications ... 6 Configuration Using the SPI ... 34 Switching Specifications .. 8 Hardware Interface ... 34 Timing Specifications .. 9 Configuration Without the SPI .. 35 Absolute Maximum Ratings .. 10 SPI Accessible Features .. 35 Thermal Characteristics .. 10 Memory Map .. 36 ESD Caution .. 10 Reading the Memory Map Register Table ... 36 Pin Configurations and Function Descriptions ... 11 Memory Map Register Table ... 37 Typical Performance Characteristics ... 15 Memory Map Register Descriptions .. 39 Equivalent Circuits ... 23 Applications Information .. 40 Theory of Operation .. 25 Design Guidelines .. 40 ADC Architecture .. 25 Outline Dimensions ... 41 Analog Input Considerations .. 25 Ordering Guide .. 41
REVISION HISTORY 8/13—Rev. B to Rev. C
Changes to Data Clock Output (DCO) Section ... 32 Changes to Ordering Guide .. 41
3/13—Rev. A to Rev. B
Changes to Table 17 .. 37 Updated Outline Dimensions ... 41
1/10—Rev. 0 to Rev. A
Changes to Worst Other (Harmonic or Spur) Parameter, Table 2 .. 5 Changes to Figure 77 .. 29 Changes to Input Clock Divider Section ... 30 Changes to Table 17 .. 37 Updated Outline Dimensions ... 41
10/09—Revision 0: Initial Version
Rev. C | Page 2 of 44 Document Outline Features Applications Product Highlights Functional Block Diagram Table of Contents Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Dither Large Signal FFT Small Signal FFT Static Linearity Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Clock Duty Cycle Input Clock Divider Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Applications Information Design Guidelines Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide
