Datasheet AD7944 (Analog Devices) - 9

ManufacturerAnalog Devices
Description14-Bit, 2.5 MSPS, PulSAR 15.5 mW ADC in LFCSP
Pages / Page29 / 9 — AD7944. Data Sheet. Pin No. Mnemonic. Type1 Description
RevisionC
File Format / SizePDF / 699 Kb
Document LanguageEnglish

AD7944. Data Sheet. Pin No. Mnemonic. Type1 Description

AD7944 Data Sheet Pin No Mnemonic Type1 Description

Model Line for this Datasheet

Text Version of Document

AD7944 Data Sheet Pin No. Mnemonic Type1 Description
19 BVDD P Reference Buffer Power. Nominally at 5.0 V. If an external reference buffer is used to achieve the maximum SNR performance with a 5 V reference, the reference buffer must be powered down by connecting the REFIN pin to ground. The external reference buffer must be connected to the BVDD pin. 20 REFIN AI/O Internal Reference Output/Reference Buffer Input. When PDREF is low, the internal band gap reference produces a 1.2 V (typical) voltage on this pin, which needs external decoupling (0.1 µF typical). When PDREF is high, use an external reference to provide 1.2 V (typical) to this pin. When PDREF is high and REFIN is low, the on-chip reference buffer and the band gap reference are powered down. An external reference must be connected to REF and BVDD. EPAD EP Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. 1 AI = analog input, AI/O = bidirectional analog, DI = digital input, DO = digital output, and P = power. Rev. C | Page 8 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION APPLICATION DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION CONVERSION MODES OF OPERATION Transfer Functions TYPICAL APPLICATION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT Internal Reference, REF = 4.096 V (PDREF Low) External 1.2 V Reference and Internal Buffer (PDREF High) External Reference (PDREF High, REFIN Low) Reference Decoupling POWER SUPPLY DIGITAL INTERFACE DATA READING OPTIONS Reading During Conversion, Fast Host (Turbo or Normal Mode) Split Reading, Any Speed Host (Turbo or Normal Mode) Reading During Acquisition, Any Speed Host (Turbo or Normal Mode) CS\ MODE, 3-WIRE WITHOUT BUSY INDICATOR CS\ MODE, 3-WIRE WITH BUSY INDICATOR CS\ MODE, 4-WIRE WITHOUT BUSY INDICATOR CS\ MODE, 4-WIRE WITH BUSY INDICATOR CHAIN MODE WITHOUT BUSY INDICATOR CHAIN MODE WITH BUSY INDICATOR APPLICATIONS INFORMATION LAYOUT EVALUATING AD7944 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE