Datasheet AD7357 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Differential Input, Dual, Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC |
| Pages / Page | 25 / 7 — AD7357. Data Sheet. TIMING SPECIFICATIONS. Table 3. Parameter. Limit at … |
| Revision | E |
| File Format / Size | PDF / 701 Kb |
| Document Language | English |
AD7357. Data Sheet. TIMING SPECIFICATIONS. Table 3. Parameter. Limit at TMIN, TMAX. Unit. Description
Model Line for this Datasheet
Text Version of Document
AD7357 Data Sheet TIMING SPECIFICATIONS
V 1 DD = 2.5 V ± 10%, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, TA = TMAX to TMIN , unless otherwise noted.
Table 3. Parameter Limit at TMIN, TMAX Unit Description
fSCLK 500 kHz min 80 MHz max tCONVERT t2 + 15.5 × tSCLK ns min tSCLK = 1/fSCLK tQUIET 5 ns min Minimum time between end of serial read and next falling edge of CS t2 5 ns min CS to SCLK setup time t 2 3 6 ns max Delay from CS until SDATAA and SDATAB are three-state disabled t 2, 3 4 Data access time after SCLK falling edge 12.5 ns max 1.8 V ≤ VDRIVE < 2.25 V 11 ns max 2.25 V ≤ VDRIVE < 2.75 V 9.5 ns max 2.75 V ≤ VDRIVE < 3.3 V 9 ns max 3.3 V ≤ VDRIVE ≤ 3.6 V t5 5 ns min SCLK low pulse width t6 5 ns min SCLK high pulse width t 2 7 SCLK to data valid hold time 3.5 ns min 1.8 V ≤ VDRIVE < 2.75 V 3 ns min 2.75 V ≤ VDRIVE ≤ 3.6 V t8 9.5 ns max CS rising edge to SDATAA, SDATAB, high impedance t9 5 ns min CS rising edge to falling edge pulse width t 2 10 4.5 ns min SCLK falling edge to SDATAA, SDATAB, high impedance 9.5 ns max SCLK falling edge to SDATAA, SDATAB, high impedance Latency 1 conversion latency 1 Temperature ranges are as follows: AD7357Y: −40°C to +125°C; AD7357B (TSSOP): −40°C to +85°C; AD7357B (LFCSP): −40°C to +125°C; AD7357WY: −40°C to +125°C. 2 Specified with a load capacitance of 10 pF on SDATAA and SDATAB. 3 The time required for the output to cross 0.4 V or 2.4 V. Rev. E | Page 6 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT STRUCTURE ANALOG INPUTS DRIVING DIFFERENTIAL INPUTS Differential Amplifier Operational Amplifier Pair VOLTAGE REFERENCE ADC TRANSFER FUNCTION MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER vs. THROUGHPUT RATE SERIAL INTERFACE APPLICATION SUGGESTIONS GROUNDING AND LAYOUT EVALUATING THE AD7357 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS
V 1 DD = 2.5 V ± 10%, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, TA = TMAX to TMIN , unless otherwise noted.
Table 3. Parameter Limit at TMIN, TMAX Unit Description
fSCLK 500 kHz min 80 MHz max tCONVERT t2 + 15.5 × tSCLK ns min tSCLK = 1/fSCLK tQUIET 5 ns min Minimum time between end of serial read and next falling edge of CS t2 5 ns min CS to SCLK setup time t 2 3 6 ns max Delay from CS until SDATAA and SDATAB are three-state disabled t 2, 3 4 Data access time after SCLK falling edge 12.5 ns max 1.8 V ≤ VDRIVE < 2.25 V 11 ns max 2.25 V ≤ VDRIVE < 2.75 V 9.5 ns max 2.75 V ≤ VDRIVE < 3.3 V 9 ns max 3.3 V ≤ VDRIVE ≤ 3.6 V t5 5 ns min SCLK low pulse width t6 5 ns min SCLK high pulse width t 2 7 SCLK to data valid hold time 3.5 ns min 1.8 V ≤ VDRIVE < 2.75 V 3 ns min 2.75 V ≤ VDRIVE ≤ 3.6 V t8 9.5 ns max CS rising edge to SDATAA, SDATAB, high impedance t9 5 ns min CS rising edge to falling edge pulse width t 2 10 4.5 ns min SCLK falling edge to SDATAA, SDATAB, high impedance 9.5 ns max SCLK falling edge to SDATAA, SDATAB, high impedance Latency 1 conversion latency 1 Temperature ranges are as follows: AD7357Y: −40°C to +125°C; AD7357B (TSSOP): −40°C to +85°C; AD7357B (LFCSP): −40°C to +125°C; AD7357WY: −40°C to +125°C. 2 Specified with a load capacitance of 10 pF on SDATAA and SDATAB. 3 The time required for the output to cross 0.4 V or 2.4 V. Rev. E | Page 6 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT STRUCTURE ANALOG INPUTS DRIVING DIFFERENTIAL INPUTS Differential Amplifier Operational Amplifier Pair VOLTAGE REFERENCE ADC TRANSFER FUNCTION MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER vs. THROUGHPUT RATE SERIAL INTERFACE APPLICATION SUGGESTIONS GROUNDING AND LAYOUT EVALUATING THE AD7357 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS
