Datasheet AD9626 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter |
| Pages / Page | 37 / 3 — AD9626. TABLE OF CONTENTS. REVISION HISTORY. 11/07—Revision 0: Initial … |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
AD9626. TABLE OF CONTENTS. REVISION HISTORY. 11/07—Revision 0: Initial Version
Model Line for this Datasheet
Text Version of Document
link to page 1 link to page 1 link to page 1 link to page 1 link to page 1 link to page 1 link to page 1 link to page 1 link to page 1 link to page 1 link to page 3 link to page 3 link to page 4 link to page 4 link to page 4 link to page 4 link to page 5 link to page 5 link to page 6 link to page 6 link to page 7 link to page 7 link to page 8 link to page 8 link to page 9 link to page 9 link to page 9 link to page 9 link to page 9 link to page 9 link to page 10 link to page 10 link to page 12 link to page 12 link to page 13 link to page 13 link to page 19 link to page 19 link to page 19 link to page 19 link to page 20 link to page 20 link to page 21 link to page 21 link to page 21 link to page 21 link to page 22 link to page 22 link to page 22 link to page 22 link to page 23 link to page 23 link to page 23 link to page 23 link to page 23 link to page 23 link to page 23 link to page 23 link to page 23 link to page 23 link to page 24 link to page 24 link to page 24 link to page 24 link to page 26 link to page 26 link to page 26 link to page 26 link to page 26 link to page 26 link to page 26 link to page 26 link to page 26 link to page 26 link to page 28 link to page 28 link to page 34 link to page 34 link to page 34 link to page 34
AD9626 TABLE OF CONTENTS
Features .. 1 Clock Input Considerations.. 19 Applications... 1 Power Dissipation and Power-Down Mode ... 20 Functional Block Diagram .. 1 Digital Outputs ... 20 General Description ... 1 Timing—Single Port Mode ... 21 Product Highlights ... 1 Timing—Interleaved Mode... 21 Revision History ... 2 Layout Considerations... 22 Specifications... 3 Power and Ground Recommendations ... 22 DC Specifications ... 3 CML ... 22 AC Specifications.. 4 RBIAS... 22 Digital Specifications ... 5 AD9626 Configuration Using the SPI ... 22 Switching Specifications .. 6 Hardware Interface... 23 Timing Diagrams.. 7 Configuration Without the SPI .. 23 Absolute Maximum Ratings.. 8 Memory Map .. 25 Thermal Resistance .. 8 Reading the Memory Map Table.. 25 ESD Caution.. 8 Reserved Locations .. 25 Pin Configurations and Function Descriptions ... 9 Default Values ... 25 Equivalent Circuits ... 11 Logic Levels... 25 Typical Performance Characteristics ... 12 Evaluation Board .. 27 Theory of Operation .. 18 Outline Dimensions ... 33 Analog Input and Voltage Reference ... 18 Ordering Guide .. 33
REVISION HISTORY 11/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Out-of-Range TIMING—SINGLE PORT MODE TIMING—INTERLEAVED MODE fS/2 Spurious LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS AD9626 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
AD9626 TABLE OF CONTENTS
Features .. 1 Clock Input Considerations.. 19 Applications... 1 Power Dissipation and Power-Down Mode ... 20 Functional Block Diagram .. 1 Digital Outputs ... 20 General Description ... 1 Timing—Single Port Mode ... 21 Product Highlights ... 1 Timing—Interleaved Mode... 21 Revision History ... 2 Layout Considerations... 22 Specifications... 3 Power and Ground Recommendations ... 22 DC Specifications ... 3 CML ... 22 AC Specifications.. 4 RBIAS... 22 Digital Specifications ... 5 AD9626 Configuration Using the SPI ... 22 Switching Specifications .. 6 Hardware Interface... 23 Timing Diagrams.. 7 Configuration Without the SPI .. 23 Absolute Maximum Ratings.. 8 Memory Map .. 25 Thermal Resistance .. 8 Reading the Memory Map Table.. 25 ESD Caution.. 8 Reserved Locations .. 25 Pin Configurations and Function Descriptions ... 9 Default Values ... 25 Equivalent Circuits ... 11 Logic Levels... 25 Typical Performance Characteristics ... 12 Evaluation Board .. 27 Theory of Operation .. 18 Outline Dimensions ... 33 Analog Input and Voltage Reference ... 18 Ordering Guide .. 33
REVISION HISTORY 11/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Out-of-Range TIMING—SINGLE PORT MODE TIMING—INTERLEAVED MODE fS/2 Spurious LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS AD9626 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
