Datasheet AD7764 (Analog Devices) - 7

AD7764 Data Sheet TIMING SPECIFICATIONS
AVDD1 = DVDD = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, VREF+ = 4.096 V, TA = 25°C, CLOAD = 25 pF.
Table
3
. Limit at TMIN, TMAX Parameter Min Typ Max Unit Description
fMCLK 500 kHz Applied master clock frequency 40 MHz fICLK 250 kHz Internal modulator clock derived from MCLK 20 MHz t1 1 × tICLK sec SCO high period t2 1 × tICLK sec SCO low period t3 1 2.5 ns SCO rising edge to FSO falling edge t4 2 3.5 ns Data access time, FSO falling edge to data active t5 8 ns MSB data access time, SDO active to SDO valid t6 40 ns Data hold time (SDO valid to SCO rising edge) t7 9.5 ns Data access time (SCO rising edge to SDO valid) t8 2 2.5 ns SCO rising edge to FSO rising edge t9 32 × tSCO sec FSO low period t10 12 ns Setup time from FSI falling edge to SCO falling edge t11 1 × tSCO sec FSI low period t 1 12 32 × tSCO sec FSI low period t13 12 ns SDI setup time for the first data bit t14 12 ns SDI setup time t15 0 ns SDI hold time tR MIN 1 × tMCLK sec Minimum time for a valid RESET pulse tR HOLD 5 ns Minimum time between the MCLK rising edge and RESET rising edge tR SETUP 5 ns Minimum time between the RESET rising edge and MCLK rising edge tS MIN 4 × tMCLK sec Minimum time for a valid SYNC pulse tS HOLD 5 ns Minimum time between the MCLK falling edge and SYNC rising edge tS SETUP 5 ns Minimum time between the SYNC rising edge and MCLK falling edge 1 This is the maximum time FSI can be held low when writing to an individual device (a device that is not daisy-chained). Rev. B | Page 6 of 33 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION Σ-Δ MODULATION AND DIGITAL FILTERING AD7764 ANTIALIAS PROTECTION INPUT STRUCTURE ON-CHIP DIFFERENTIAL AMPLIFIER MODULATOR INPUT STRUCTURE DRIVING THE MODULATOR INPUTS DIRECTLY AD7764 SERIAL INTERFACE READING DATA READING STATUS AND OTHER REGISTERS WRITING TO THE AD7764 FUNCTIONALITY SYNCHRONIZATION OVERRANGE ALERTS POWER MODES Low Power Mode RESETB/PWRDWNB Mode DECIMATION RATE PIN DAISY-CHAINING READING DATA IN DAISY-CHAIN MODE WRITING DATA IN DAISY-CHAIN MODE CLOCKING THE AD7764 MCLK JITTER REQUIREMENTS Example 1 Example 2 DECOUPLING AND LAYOUT INFORMATION SUPPLY DECOUPLING REFERENCE VOLTAGE FILTERING DIFFERENTIAL AMPLIFIER COMPONENTS LAYOUT CONSIDERATIONS USING THE AD7764 BIAS RESISTOR SELECTION AD7764 REGISTERS CONTROL REGISTER STATUS REGISTER GAIN REGISTER—ADDRESS 0x0004 Nonbit Mapped, Default Value: 0xA000 OVERRANGE REGISTER—ADDRESS 0x0005 Nonbit Mapped, Default Value: 0xCCCC OUTLINE DIMENSIONS ORDERING GUIDE