Datasheet AD7764 (Analog Devices) - 6

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Data Sheet AD7764 Parameter Test Conditions/Comments Min Typ Max Unit
DIGITAL INPUT/OUTPUT MCLK Input Amplitude 2.25 5.25 V Input Capacitance 7.3 pF Input Leakage Current ±1 μA/pin VINH 0.8 × V DVDD VINL 0.2 × DVDD V V 4 OH 2.2 V VOL 0.1 V ON-CHIP DIFFERENTIAL AMPLIFIER Input Impedance >1 MΩ Bandwidth for 0.1 dB Flatness 125 kHz Common-Mode Input Voltage5 Common-mode voltage at amplifier input pins; 0.8 2.2 V VINA+ and VINA− Common-Mode Output Voltage On-chip differential amplifier pins, VOUTA+ and 2.048 V VOUTA− POWER REQUIREMENTS AVDD1 (Modulator Supply) 2.375 2.625 V AVDD2 (General Supply) 4.75 5.25 V AVDD3 (Differential Amplifier Supply) 5 V supply required for 4.096 V reference 3.15 5.25 V AVDD4 (Reference Buffer Supply) 5 V supply required for 4.096 V reference 3.15 5.25 V min/ max DVDD ±5% 2.375 2.625 V Normal Power Mode AIDD1 (Modulator) 19 mA AIDD2 (General)6 MCLK = 40 MHz 13 mA AIDD3 (Differential Amplifier) AVDD3 = 5 V 10 mA AIDD4 (Reference Buffer) AVDD4 = 5 V 9 mA DI 6 DD MCLK = 40 MHz 37 mA Low Power Mode AIDD1 (Modulator) 10 mA AI 6 DD2 (General) MCLK = 40 MHz 7 mA AIDD3 (Differential Amplifier) AVDD3 = 5 V 5.5 mA AIDD4 (Reference Buffer) AVDD4 = 5 V 5 mA DI 6 DD MCLK = 40 MHz 20 mA POWER DISSIPATION Normal Power Mode MCLK = 40 MHz, decimate 64× 300 371 mW Low Power Mode MCLK = 40 MHz, decimate 64× 160 215 mW Power-Down Mode7 PWRDWN pin held logic low 1 mW 1 See the Terminology section. 2 SNR specifications in decibels are referred to a full-scale input, FS, and are tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 3 The output data rate (ODR) = [(MCLK/2)]/decimation rate. That is, the maximum ODR for the AD7764 = [(40 MHz)/2)/64] = 312.5 kHz. 4 Tested with a 400 µA load current. 5 Specified min and max values relate to the common mode voltage at which the protection circuitry on the pins (VINA+ and VINA−) starts to turn on. Prior to this turn on, the THD of the AD7764 degrades at common modes approaching 2 V, or on the lower side approaching 1 V. 6 Tested at MCLK = 40 MHz. This current scales linearly with the applied MCLK frequency. 7 Tested at 125°C. Rev. B | Page 5 of 33 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION Σ-Δ MODULATION AND DIGITAL FILTERING AD7764 ANTIALIAS PROTECTION INPUT STRUCTURE ON-CHIP DIFFERENTIAL AMPLIFIER MODULATOR INPUT STRUCTURE DRIVING THE MODULATOR INPUTS DIRECTLY AD7764 SERIAL INTERFACE READING DATA READING STATUS AND OTHER REGISTERS WRITING TO THE AD7764 FUNCTIONALITY SYNCHRONIZATION OVERRANGE ALERTS POWER MODES Low Power Mode RESETB/PWRDWNB Mode DECIMATION RATE PIN DAISY-CHAINING READING DATA IN DAISY-CHAIN MODE WRITING DATA IN DAISY-CHAIN MODE CLOCKING THE AD7764 MCLK JITTER REQUIREMENTS Example 1 Example 2 DECOUPLING AND LAYOUT INFORMATION SUPPLY DECOUPLING REFERENCE VOLTAGE FILTERING DIFFERENTIAL AMPLIFIER COMPONENTS LAYOUT CONSIDERATIONS USING THE AD7764 BIAS RESISTOR SELECTION AD7764 REGISTERS CONTROL REGISTER STATUS REGISTER GAIN REGISTER—ADDRESS 0x0004 Nonbit Mapped, Default Value: 0xA000 OVERRANGE REGISTER—ADDRESS 0x0005 Nonbit Mapped, Default Value: 0xCCCC OUTLINE DIMENSIONS ORDERING GUIDE