Datasheet AD9211 (Analog Devices)

10-Bit, 200 MSPS/250 MSPS/300 MSPS, 1.8 V Analog-to-Digital Converter AD9211 FEATURES FUNCTIONAL BLOCK DIAGRAM RBIAS PWDN AGND AVDD (1.8V) SNR = 60.1 dBFS @ fIN up to 70 MHz @ 300 MSPS ENOB of 9.7 @ fIN up to 70 MHz @ 300 MSPS (−1.0 dBFS) REFERENCE AD9211 SFDR = −80 dBc @ fIN up to 70 MHz @ 300 MSPS (−1.0 dBFS) Excellent linearity DRVDD DGND DNL = ±0.1 LSB typical VIN+ TRACK-AND-HOLD VIN– INL = ±0.2 LSB typical ADC 10 OUTPUT 10 LVDS at 300 MSPS (ANSI-644 levels) 10-BIT STAGING D9 TO D0 CORE LVDS 700 MHz full power analog bandwidth CLK+ CLOCK OR+ On-chip reference, no external decoupling required CLK– MANAGEMENT OR– Integrated input buffer and track-and-hold SERIAL PORT Low power dissipation DCO+ DCO– 437 mW @ 300 MSPS—LVDS SDR mode
001
410 mW @ 300 MSPS—LVDS DDR mode RESET SCLK SDIO CSB
6041- 0
Programmable input voltage range
Figure 1.
1.0 V to 1.5 V, 1.25 V nominal 1.8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, Gray code) Clock duty cycle stabilizer Integrated data capture clock APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
The AD9211 is a 10-bit monolithic sampling analog-to-digital 1. High Performance—Maintains 60.1 dBFS SNR @ converter optimized for high performance, low power, and ease 300 MSPS with a 70 MHz input. of use. The product operates at up to a 300 MSPS conversion 2. Low Power—Consumes only 410 mW @ 300 MSPS. rate and is optimized for outstanding dynamic performance 3. Ease of Use—LVDS output data and output clock signal in wideband carrier and broadband systems. All necessary allow interface to current FPGA technology. The on-chip functions, including a track-and-hold (T/H) and voltage reference and sample-and-hold provide flexibility in reference, are included on the chip to provide a complete system design. Use of a single 1.8 V supply simplifies signal conversion solution. system power supply design. The ADC requires a 1.8 V analog voltage supply and a 4. Serial Port Control—Standard serial port interface differential clock for full performance operation. The digital supports various product functions, such as data outputs are LVDS (ANSI-644) compatible and support either formatting, disabling the clock duty cycle stabilizer, power- twos complement, offset binary format, or Gray code. A data down, gain adjust, and output test pattern generation. clock output is available for proper output data timing. 5. Pin-Compatible Family—12-bit pin-compatible family offered as AD9230. Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C).
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS AD9211 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE