Datasheet AD7952 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 14-Bit, 1 MSPS, Differential, Programmable Input PulSAR® ADC |
| Pages / Page | 33 / 6 — Data Sheet. AD7952. TIMING SPECIFICATIONS. Table 3. Parameter Symbol. … |
| Revision | A |
| File Format / Size | PDF / 615 Kb |
| Document Language | English |
Data Sheet. AD7952. TIMING SPECIFICATIONS. Table 3. Parameter Symbol. Min. Typ. Max. Unit
Model Line for this Datasheet
Text Version of Document
link to page 24 link to page 25 link to page 7 link to page 25 link to page 25 link to page 7 link to page 27 link to page 27 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7
Data Sheet AD7952 TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (See Figure 34 and Figure 35) Convert Pulse Width t1 10 ns Time Between Conversions t2 Warp Mode/Normal Mode/Impulse Mode1 1/1.25/1.49 μs CNVST Low to BUSY High Delay t3 35 ns BUSY High All Modes (Except Master Serial Read After Convert) t4 Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns Aperture Delay t5 2 ns End of Conversion to BUSY Low Delay t6 10 ns Conversion Time t7 Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns Acquisition Time t8 Warp Mode/Normal Mode/Impulse Mode 200 ns RESET Pulse Width t9 10 ns PARALLEL INTERFACE MODES (See Figure 36 and Figure 38) CNVST Low to DATA Valid Delay t10 Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns DATA Valid to BUSY Low Delay t11 20 ns Bus Access Request to DATA Valid t12 40 ns Bus Relinquish Time t13 2 15 ns MASTER SERIAL INTERFACE MODES2 (See Figure 40 and Figure 41) CS Low to SYNC Valid Delay t14 10 ns CS Low to Internal SDCLK Valid Delay2 t15 10 ns CS Low to SDOUT Delay t16 10 ns CNVST Low to SYNC Delay, Read During Convert t17 Warp Mode/Normal Mode/Impulse Mode 50/290/530 ns SYNC Asserted to SDCLK First Edge Delay t18 3 ns Internal SDCLK Period3 t19 30 45 ns Internal SDCLK High3 t20 15 ns Internal SDCLK Low3 t21 10 ns SDOUT Valid Setup Time3 t22 4 ns SDOUT Valid Hold Time3 t23 5 ns SDCLK Last Edge to SYNC Delay3 t24 5 ns CS High to SYNC High-Z t25 10 ns CS High to Internal SDCLK High-Z t26 10 ns CS High to SDOUT High-Z t27 10 ns BUSY High in Master Serial Read After Convert3 t28 See Table 4 CNVST Low to SYNC Delay, Read After Convert t29 Warp Mode/Normal Mode/Impulse Mode 710/950/1190 ns SYNC Deasserted to BUSY Low Delay t30 25 ns Rev. A | Page 5 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION OVERVIEW CONVERTER OPERATION MODES OF OPERATION Warp Mode Normal Mode Impulse Mode TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS Input Range Selection Input Structure Single-to-Differential Driver VOLTAGE REFERENCE INPUT/OUTPUT Internal Reference (REF = 5 V, PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V, PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor POWER SUPPLIES Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) SERIAL INTERFACE Data Interface Serial Configuration Interface MASTER SERIAL INTERFACE Internal Clock (SER/ = High, EXT/ = Low) Read During Convert (RDC = High) Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) SLAVE SERIAL INTERFACE External Clock (SER/ = High, EXT/ = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion HARDWARE CONFIGURATION SOFTWARE CONFIGURATION MICROPROCESSOR INTERFACING SPI Interface APPLICATION INFORMATION LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7952 TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (See Figure 34 and Figure 35) Convert Pulse Width t1 10 ns Time Between Conversions t2 Warp Mode/Normal Mode/Impulse Mode1 1/1.25/1.49 μs CNVST Low to BUSY High Delay t3 35 ns BUSY High All Modes (Except Master Serial Read After Convert) t4 Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns Aperture Delay t5 2 ns End of Conversion to BUSY Low Delay t6 10 ns Conversion Time t7 Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns Acquisition Time t8 Warp Mode/Normal Mode/Impulse Mode 200 ns RESET Pulse Width t9 10 ns PARALLEL INTERFACE MODES (See Figure 36 and Figure 38) CNVST Low to DATA Valid Delay t10 Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns DATA Valid to BUSY Low Delay t11 20 ns Bus Access Request to DATA Valid t12 40 ns Bus Relinquish Time t13 2 15 ns MASTER SERIAL INTERFACE MODES2 (See Figure 40 and Figure 41) CS Low to SYNC Valid Delay t14 10 ns CS Low to Internal SDCLK Valid Delay2 t15 10 ns CS Low to SDOUT Delay t16 10 ns CNVST Low to SYNC Delay, Read During Convert t17 Warp Mode/Normal Mode/Impulse Mode 50/290/530 ns SYNC Asserted to SDCLK First Edge Delay t18 3 ns Internal SDCLK Period3 t19 30 45 ns Internal SDCLK High3 t20 15 ns Internal SDCLK Low3 t21 10 ns SDOUT Valid Setup Time3 t22 4 ns SDOUT Valid Hold Time3 t23 5 ns SDCLK Last Edge to SYNC Delay3 t24 5 ns CS High to SYNC High-Z t25 10 ns CS High to Internal SDCLK High-Z t26 10 ns CS High to SDOUT High-Z t27 10 ns BUSY High in Master Serial Read After Convert3 t28 See Table 4 CNVST Low to SYNC Delay, Read After Convert t29 Warp Mode/Normal Mode/Impulse Mode 710/950/1190 ns SYNC Deasserted to BUSY Low Delay t30 25 ns Rev. A | Page 5 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION OVERVIEW CONVERTER OPERATION MODES OF OPERATION Warp Mode Normal Mode Impulse Mode TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS Input Range Selection Input Structure Single-to-Differential Driver VOLTAGE REFERENCE INPUT/OUTPUT Internal Reference (REF = 5 V, PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V, PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor POWER SUPPLIES Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) SERIAL INTERFACE Data Interface Serial Configuration Interface MASTER SERIAL INTERFACE Internal Clock (SER/ = High, EXT/ = Low) Read During Convert (RDC = High) Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) SLAVE SERIAL INTERFACE External Clock (SER/ = High, EXT/ = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion HARDWARE CONFIGURATION SOFTWARE CONFIGURATION MICROPROCESSOR INTERFACING SPI Interface APPLICATION INFORMATION LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE
