Datasheet AD7952 (Analog Devices) - 7

link to page 7 link to page 29 link to page 29 link to page 31 link to page 7
AD7952 Data Sheet Parameter Symbol Min Typ Max Unit
SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES2 (See Figure 43, Figure 44, and Figure 46) External SDCLK, SCCLK Setup Time t31 5 ns External SDCLK Active Edge to SDOUT Delay t32 2 18 ns SDIN/SCIN Setup Time t33 5 ns SDIN/SCIN Hold Time t34 5 ns External SDCLK/SCCLK Period t35 25 ns External SDCLK/SCCLK High t36 10 ns External SDCLK/SCCLK Low t37 10 ns 1 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time. 2 In serial interface modes, the SYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 3 In serial master read during convert mode. See Table 4 for serial master read after convert mode.
Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SDCLK First Edge Delay Minimum t18 3 20 20 20 ns Internal SDCLK Period Minimum t19 30 60 120 240 ns Internal SDCLK Period Maximum t19 45 90 180 360 ns Internal SDCLK High Minimum t20 12 30 60 120 ns Internal SDCLK Low Minimum t21 10 25 55 115 ns SDOUT Valid Setup Time Minimum t22 4 20 20 20 ns SDOUT Valid Hold Time Minimum t23 5 8 35 90 ns SDCLK Last Edge to SYNC Delay Minimum t24 5 7 35 90 ns BUSY High Width Maximum t28 Warp Mode 1.60 2.35 3.75 6.75 μs Normal Mode 1.85 2.60 4.00 7.00 μs Impulse Mode 2.10 2.85 4.25 7.25 μs
1.6mA IOL TO OUTPUT 1.4V PIN C 2V L 60pF 0.8V tDELAY tDELAY 500µA IOH
3
2V 2V
-00 9
NOTES 0.8V 0.8V
58
1. IN SERIAL INTERFACE MODES, THE SYNC, SDCLK, AND
06
SDOUT ARE DEFINED WITH A MAXIMUM LOAD
02 -0
C
89
L OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
65 0 Figure 2. Load Circuit for Digital Interface Timing, Figure 3. Voltage Reference Levels for Timing SDOUT, SYNC, and SDCLK Outputs, CL = 10 pF Rev. A | Page 6 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION OVERVIEW CONVERTER OPERATION MODES OF OPERATION Warp Mode Normal Mode Impulse Mode TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS Input Range Selection Input Structure Single-to-Differential Driver VOLTAGE REFERENCE INPUT/OUTPUT Internal Reference (REF = 5 V, PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V, PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor POWER SUPPLIES Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) SERIAL INTERFACE Data Interface Serial Configuration Interface MASTER SERIAL INTERFACE Internal Clock (SER/ = High, EXT/ = Low) Read During Convert (RDC = High) Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) SLAVE SERIAL INTERFACE External Clock (SER/ = High, EXT/ = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion HARDWARE CONFIGURATION SOFTWARE CONFIGURATION MICROPROCESSOR INTERFACING SPI Interface APPLICATION INFORMATION LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE