Datasheet AD7952 (Analog Devices) - 8

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Data Sheet AD7952 ABSOLUTE MAXIMUM RATINGS Table 5.
Stresses above those listed under Absolute Maximum Ratings
Parameter Rating
may cause permanent damage to the device. This is a stress Analog Inputs/Outputs rating only; functional operation of the device at these or any IN+1, IN−1 to AGND VEE − 0.3 V to VCC + 0.3 V other conditions above those indicated in the operational REF, REFBUFIN, TEMP, AVDD + 0.3 V to REFGND to AGND AGND − 0.3 V section of this specification is not implied. Exposure to absolute Ground Voltage Differences maximum rating conditions for extended periods may affect AGND, DGND, OGND ±0.3 V device reliability. Supply Voltages AVDD, DVDD, OVDD −0.3 V to +7 V AVDD to DVDD, AVDD to OVDD ±7 V
ESD CAUTION
DVDD to OVDD ±7 V VCC to AGND, DGND –0.3 V to +16.5 V VEE to GND +0.3 V to −16.5 V Digital Inputs −0.3 V to OVDD + 0.3 V PDREF, PDBUF ±20 mA Internal Power Dissipation2 700 mW Internal Power Dissipation3 2.5 W Junction Temperature 125°C Storage Temperature Range −65°C to +125°C 1 See the Analog Inputs section. 2 Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W. 3 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W. Rev. A | Page 7 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION OVERVIEW CONVERTER OPERATION MODES OF OPERATION Warp Mode Normal Mode Impulse Mode TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS Input Range Selection Input Structure Single-to-Differential Driver VOLTAGE REFERENCE INPUT/OUTPUT Internal Reference (REF = 5 V, PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V, PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor POWER SUPPLIES Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) SERIAL INTERFACE Data Interface Serial Configuration Interface MASTER SERIAL INTERFACE Internal Clock (SER/ = High, EXT/ = Low) Read During Convert (RDC = High) Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) SLAVE SERIAL INTERFACE External Clock (SER/ = High, EXT/ = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion HARDWARE CONFIGURATION SOFTWARE CONFIGURATION MICROPROCESSOR INTERFACING SPI Interface APPLICATION INFORMATION LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE