Datasheet AD9259 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V ADC |
| Pages / Page | 53 / 8 — Data Sheet. AD9259. SWITCHING SPECIFICATIONS. Table 4. Parameter. Temp. … |
| Revision | E |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
Data Sheet. AD9259. SWITCHING SPECIFICATIONS. Table 4. Parameter. Temp. Min. Typ. Max. Unit
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Data Sheet AD9259 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4. Parameter 1 , 2 Temp Min Typ Max Unit
CLOCK3 Maximum Clock Rate Full 50 MSPS Minimum Clock Rate Full 10 MSPS Clock Pulse Width High (tEH) Full 10 ns Clock Pulse Width Low (tEL) Full 10 ns OUTPUT PARAMETERS3 Propagation Delay (tPD) Full 2.0 2.7 3.5 ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps FCO Propagation Delay (tFCO) Full 2.0 2.7 3.5 ns DCO Propagation Delay (tCPD)4 Full tFCO + ns (tSAMPLE/28) DCO to Data Delay (tDATA)4 Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps DCO to FCO Delay (tFRAME)4 Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps Data to Data Skew Full ±50 ±150 ps (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby) 25°C 600 ns Wake-Up Time (Power-Down) 25°C 375 μs Pipeline Latency Full 8 CLK cycles APERTURE Aperture Delay (tA) 25°C 500 ps Aperture Uncertainty (Jitter) 25°C <1 ps rms Out-of-Range Recovery Time 25°C 2 CLK cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 Can be adjusted via the SPI. 4 tSAMPLE/28 is based on the number of bits multiplied by 2; delays are based on half duty cycles. Rev. E | Page 7 of 52 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide
Data Sheet AD9259 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4. Parameter 1 , 2 Temp Min Typ Max Unit
CLOCK3 Maximum Clock Rate Full 50 MSPS Minimum Clock Rate Full 10 MSPS Clock Pulse Width High (tEH) Full 10 ns Clock Pulse Width Low (tEL) Full 10 ns OUTPUT PARAMETERS3 Propagation Delay (tPD) Full 2.0 2.7 3.5 ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps FCO Propagation Delay (tFCO) Full 2.0 2.7 3.5 ns DCO Propagation Delay (tCPD)4 Full tFCO + ns (tSAMPLE/28) DCO to Data Delay (tDATA)4 Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps DCO to FCO Delay (tFRAME)4 Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps Data to Data Skew Full ±50 ±150 ps (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby) 25°C 600 ns Wake-Up Time (Power-Down) 25°C 375 μs Pipeline Latency Full 8 CLK cycles APERTURE Aperture Delay (tA) 25°C 500 ps Aperture Uncertainty (Jitter) 25°C <1 ps rms Out-of-Range Recovery Time 25°C 2 CLK cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 Can be adjusted via the SPI. 4 tSAMPLE/28 is based on the number of bits multiplied by 2; delays are based on half duty cycles. Rev. E | Page 7 of 52 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide
