Datasheet AD9446 (Analog Devices) - 10

AD9446 TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) Minimum Conversion Rate
The analog input frequency at which the spectral power of the The clock rate at which the SNR of the lowest analog signal fundamental frequency (as determined by the FFT analysis) is frequency drops by no more than 3 dB below the guaranteed reduced by 3 dB. limit.
Aperture Delay (tA) Offset Error
The delay between the 50% point of the rising edge of the clock The major carry transition should occur for an analog value of and the instant at which the analog input is sampled. ½ LSB below VIN+ = VIN−. Offset error is defined as the deviation of the actual transition from that point.
Aperture Uncertainty (Jitter, tJ)
The sample-to-sample variation in aperture delay.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
Clock Pulse Width and Duty Cycle
after a transition from 10% above positive full scale to 10% Pulse width high is the minimum amount of time that the above negative full scale, or from 10% below negative full scale clock pulse should be left in the Logic 1 state to achieve rated to 10% below positive full scale. performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these
Output Propagation Delay (tPD)
specifications define an acceptable clock duty cycle. The delay between the clock rising edge and the time when all bits are within valid logic levels.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
Power-Supply Rejection Ratio
apart. DNL is the deviation from this ideal value. Guaranteed The change in full scale from the value with the supply at the no missing codes to 16-bit resolution indicates that all 65,536 minimum limit to the value with the supply at the maximum codes must be present over all operating ranges. limit.
Effective Number of Bits (ENOB) Signal-to-Noise and Distortion (SINAD)
The effective number of bits for a sine wave input at a given The ratio of the rms input signal amplitude to the rms value of input frequency can be calculated directly from its measured the sum of all other spectral components below the Nyquist SINAD using the following formula: frequency, including harmonics but excluding dc. ( −1.76) = SINAD ENOB
Signal-to-Noise Ratio (SNR)
6.02 The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist
Gain Error
frequency, excluding the first six harmonics and dc. The first code transition should occur at an analog value of ½ LSB above negative full scale. The last transition should occur
Spurious-Free Dynamic Range (SFDR)
at an analog value of 1½ LSB below the positive full scale. Gain The ratio of the rms signal amplitude to the rms value of the error is the deviation of the actual difference between first and peak spurious spectral component. The peak spurious component last code transitions and the ideal difference between first and may be a harmonic. SFDR can be reported in dBc (that is, degrades last code transitions. as signal level is lowered) or dBFS (always related back to converter full scale).
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
Temperature Drift
negative full scale through positive full scale. The point used as The temperature drift for offset error and gain error specifies negative full scale occurs ½ LSB before the first code transition. the maximum change from the initial (25°C) value to the value Positive full scale is defined as a level 1½ LSB beyond the last at TMIN or TMAX. code transition. The deviation is measured from the middle of each particular code to the true straight line.
Total Harmonic Distortion (THD)
The ratio of the rms input signal amplitude to the rms value of
Maximum Conversion Rate
the sum of the first six harmonic components. The clock rate at which parametric testing is performed.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Rev. 0 | Page 9 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TERMINOLOGY PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE