Datasheet AD7762 (Analog Devices) - 4

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Data Sheet AD7762 SPECIFICATIONS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, VREF = 4.096 V, MCLK amplitude = 5 V, TA = 25°C, normal mode, using on-chip amplifier with components as shown in Table 8, unless otherwise noted.1
Table 2. Parameter Test Conditions/Comments Specification Unit
DYNAMIC PERFORMANCE Decimate by 256 MCLK = 40 MHz, ODR = 78 kHz, FIN = 1 kHz Dynamic Range Modulator inputs shorted 119 dB min 120.5 dB typ Signal-to-Noise Ratio (SNR)2 Input amplitude = −0.5 dBFS 112 dB typ Input amplitude = −60 dBFS 59 dB typ Spurious-Free Dynamic Range (SFDR) Nonharmonic, input amplitude = −6 dBFS 126 dBc typ Input amplitude = −60 dBFS 77 dBc typ Total Harmonic Distortion (THD) Input amplitude = −0.5 dBFS −105 dB typ Input amplitude = −6 dBFS −106 dB typ Input amplitude = −60 dBFS −75 dB typ Decimate by 64 MCLK = 40 MHz, ODR = 312.5 kHz, FIN = 1 kHz Dynamic Range Modulator inputs shorted 112 dB min 114 dB typ Signal-to-Noise Ratio (SNR)2 Input amplitude = −0.5 dBFS 109.5 dB typ Spurious-Free Dynamic Range (SFDR) Nonharmonic, input amplitude = −6 dBFS 126 dBc typ Decimate by 32 MCLK = 40 MHz, ODR = 625 kHz, FIN =100 kHz Dynamic Range Modulator inputs shorted 108 dB min 109.5 dB typ Signal-to-Noise Ratio (SNR)2 Input amplitude = −0.5 dBFS 107 dB typ Spurious-Free Dynamic Range (SFDR) Nonharmonic, input amplitude = −6 dBFS 120 dBc typ Total Harmonic Distortion (THD) Input amplitude = −0.5 dBFS −108 dB typ Input amplitude = −6 dBFS −106 dB typ DC ACCURACY Resolution 24 Bits Differential Nonlinearity Guaranteed monotonic to 24 bits Integral Nonlinearity 0.00076 % typ Zero Error 0.014 % typ 0.02 % max Gain Error 0.015 % typ Zero Error Drift 0.019 %/°C typ Gain Error Drift 0.0002 %/°C typ DIGITAL FILTER RESPONSE Decimate by 32 Group Delay MCLK = 40 MHz 47 µs typ Decimate by 64 Group Delay MCLK = 40 MHz 91.5 µs typ Decimate by 256 Group Delay MCLK = 40 MHz 358 µs typ ANALOG INPUT Differential Input Voltage VIN(+) – VIN(−), VREF = 2.5 V ±2 V p-p VIN(+) – VIN(−), VREF = 4.096 V ±3.25 V p-p Input Capacitance At internal buffer inputs 5 pF typ At modulator inputs 55 pF typ Rev. A | Page 3 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Theory of Operation AD7762 Interface Reading Data Sharing the Parallel Bus Writing to the AD7762 Reading Status and Other Registers Clocking the AD7762 Example 1 Example 2 Driving the AD7762 Using the AD7762 Bias Resistor Selection Decoupling and Layout Recommendations Supply Decoupling Additional Decoupling Reference Voltage Filtering Differential Amplifier Components Layout Considerations Programmable FIR Filter Downloading a User-Defined Filter Example Filter Download AD7762 Registers Control Register 1—Reg 0x0001 Default Value 0x001A Control Register 2—Address 0x0002 Default Value 0x009B Status Register (Read Only) Offset Register—Address 0x0003 Non-bitmapped, Default Value 0x0000 Gain Register—Address 0x0004 Non-bitmapped, Default Value 0xA000 Overrange Register—Address 0x0005 Non-bitmapped, Default Value 0xCCCC Outline Dimensions Ordering Guide